Mesa (master): radv: move shader stages calculation to pipeline.
Dave Airlie
airlied at kemper.freedesktop.org
Tue Mar 28 07:41:00 UTC 2017
Module: Mesa
Branch: master
Commit: 239a9224a33d280cd5703c29ce6eb9df2eab9b3d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=239a9224a33d280cd5703c29ce6eb9df2eab9b3d
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Mar 28 12:59:17 2017 +1000
radv: move shader stages calculation to pipeline.
With tess this becomes a bit more complex. so move to pipeline
for now.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 9 +--------
src/amd/vulkan/radv_pipeline.c | 9 ++++++++-
src/amd/vulkan/radv_private.h | 1 +
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 04c28d6a29..e994df65fd 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1286,14 +1286,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
}
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
- uint32_t stages = 0;
-
- if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
- stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
- S_028B54_GS_EN(1) |
- S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
-
- radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
+ radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 252808d7a7..07020e8c38 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1771,7 +1771,14 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
calculate_pa_cl_vs_out_cntl(pipeline);
calculate_ps_inputs(pipeline);
-
+
+ uint32_t stages = 0;
+ if (radv_pipeline_has_gs(pipeline))
+ stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
+ S_028B54_GS_EN(1) |
+ S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
+ pipeline->graphics.vgt_shader_stages_en = stages;
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 0b8c86df79..f587ee3ffd 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -965,6 +965,7 @@ struct radv_pipeline {
uint32_t ps_input_cntl[32];
uint32_t ps_input_cntl_num;
uint32_t pa_cl_vs_out_cntl;
+ uint32_t vgt_shader_stages_en;
struct radv_prim_vertex_count prim_vertex_count;
} graphics;
};
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