Mesa (master): anv: Require vertex buffers to come from a 32-bit heap
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Wed May 24 00:35:22 UTC 2017
Module: Mesa
Branch: master
Commit: d7e4361745a12ad2bbb35ce3a43496d0d110fa30
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7e4361745a12ad2bbb35ce3a43496d0d110fa30
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 17 11:54:24 2017 -0700
anv: Require vertex buffers to come from a 32-bit heap
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Cc: "17.1" <mesa-stable at lists.freedesktop.org>
---
src/intel/vulkan/anv_device.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index b0fca78252..501f0571dd 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -153,6 +153,18 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) {
uint32_t valid_buffer_usage = ~0;
+ /* There appears to be a hardware issue in the VF cache where it only
+ * considers the bottom 32 bits of memory addresses. If you happen to
+ * have two vertex buffers which get placed exactly 4 GiB apart and use
+ * them in back-to-back draw calls, you can get collisions. In order to
+ * solve this problem, we require vertex and index buffers be bound to
+ * memory allocated out of the 32-bit heap.
+ */
+ if (device->memory.heaps[heap].supports_48bit_addresses) {
+ valid_buffer_usage &= ~(VK_BUFFER_USAGE_INDEX_BUFFER_BIT |
+ VK_BUFFER_USAGE_VERTEX_BUFFER_BIT);
+ }
+
if (device->info.has_llc) {
/* Big core GPUs share LLC with the CPU and thus one memory type can be
* both cached and coherent at the same time.
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