Mesa (master): radv: Reserve space for descriptor and push constant user SGPR setting.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 18efb404cfb38f722a16df7539390cf9a4a71929
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=18efb404cfb38f722a16df7539390cf9a4a71929

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Mon May 29 00:18:56 2017 +0200

radv: Reserve space for descriptor and push constant user SGPR setting.

flush_compute_state doesn't reserve a large chunk, so these need their own reservation.

Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"

---

 src/amd/vulkan/radv_cmd_buffer.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index eff0fd68c9..66610e5233 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1364,6 +1364,10 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
 		radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
 	}
 
+	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
+	                                                   cmd_buffer->cs,
+	                                                   MAX_SETS * MESA_SHADER_STAGES * 4);
+
 	for (i = 0; i < MAX_SETS; i++) {
 		if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
 			continue;
@@ -1375,6 +1379,7 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
 	}
 	cmd_buffer->state.descriptors_dirty = 0;
 	cmd_buffer->state.push_descriptors_dirty = false;
+	assert(cmd_buffer->cs->cdw <= cdw_max);
 }
 
 static void
@@ -1403,6 +1408,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
 	va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
 	va += offset;
 
+	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
+	                                                   cmd_buffer->cs, MESA_SHADER_STAGES * 4);
 	if (stages & VK_SHADER_STAGE_VERTEX_BIT)
 		radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
 					   AC_UD_PUSH_CONSTANTS, va);
@@ -1428,6 +1435,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
 					   AC_UD_PUSH_CONSTANTS, va);
 
 	cmd_buffer->push_constant_stages &= ~stages;
+	assert(cmd_buffer->cs->cdw <= cdw_max);
 }
 
 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,