Mesa (master): i965/gen10: Implement Wa3DStateMode

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: 898e5555deedad71ecc5c6ce2bb2b05604e2de75
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=898e5555deedad71ecc5c6ce2bb2b05604e2de75

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Tue Sep 12 16:05:06 2017 -0700

i965/gen10: Implement Wa3DStateMode

This workaround doesn't fix any of the piglit hangs we've seen
on CNL. But it might be fixing something we haven't tested yet.

V2: Remove the bits enabling Float blend optimization. It is
    enabled through CACHE_MODE_SS register.
    Update the comment.
    Move gen10 if block on top of gen9 if block.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

---

 src/mesa/drivers/dri/i965/brw_defines.h      |  2 ++
 src/mesa/drivers/dri/i965/brw_state_upload.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 105fff3548..26f6ae6b2f 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1333,6 +1333,8 @@ enum brw_pixel_shader_coverage_mask_mode {
 /* DW2: start address */
 /* DW3: end address. */
 
+#define _3DSTATE_3D_MODE                     0x791e
+
 #define CMD_MI_FLUSH                  0x0200
 
 # define BLT_X_SHIFT					0
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9e64213c2e..f54e15e92b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -66,6 +66,20 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
                               REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
                               GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
+      /* From gen10 workaround table in h/w specs:
+       *
+       *    "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
+       *     a value of 0xFFFF"
+       *
+       * This means that we end up setting the entire 3D_MODE state. Bits
+       * in this register control things such as slice hashing and we want
+       * the default values of zero at the moment.
+       */
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
+      OUT_BATCH(0xFFFF << 16);
+      ADVANCE_BATCH();
    }
 
    if (devinfo->gen == 9) {