Mesa (master): i965/blorp: Add more destination flushing

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: d6d0ac95d5d77bd18b2064c3ed9aad70cf38cb6f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6d0ac95d5d77bd18b2064c3ed9aad70cf38cb6f

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Nov  3 16:03:52 2017 -0700

i965/blorp: Add more destination flushing

Right now we just always flush the destination for render and aren't
particularly careful about depth or stencil.  Soon, flush_for_render
isn't going to do the same thing as flush_for_depth and we may be doing
a good deal less depth flushing so we should be a bit more precise.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/genX_blorp_exec.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 2616f759ac..8411753141 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -226,7 +226,12 @@ genX(blorp_exec)(struct blorp_batch *batch,
     */
    if (params->src.enabled)
       brw_cache_flush_for_read(brw, params->src.addr.buffer);
-   brw_cache_flush_for_render(brw, params->dst.addr.buffer);
+   if (params->dst.enabled)
+      brw_cache_flush_for_render(brw, params->dst.addr.buffer);
+   if (params->depth.enabled)
+      brw_cache_flush_for_depth(brw, params->depth.addr.buffer);
+   if (params->stencil.enabled)
+      brw_cache_flush_for_depth(brw, params->stencil.addr.buffer);
    brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
 
    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);