Mesa (master): i965/vec4: fix splitting of interleaved attributes

[Iago Toral Quiroga]

Module: Mesa
Branch: master
Commit: f1873956dbbde78a9e4fb2df3cd2049891740bba
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1873956dbbde78a9e4fb2df3cd2049891740bba

Author: Iago Toral Quiroga <itoral at igalia.com>
Date:   Tue Nov 21 11:33:53 2017 +0100

i965/vec4: fix splitting of interleaved attributes

When we split an instruction that reads an uniform value
(vstride 0) we need to respect the vstride on the second
half of the instruction (that is, the second half should
read the same region as the first).

We were doing this already, but we didn't account for
stages that have interleaved input attributes which also
have a vstride of 0 and need the same treatment.

Fixes the following on Haswell:
KHR-GL45.enhanced_layouts.varying_locations
KHR-GL45.enhanced_layouts.varying_array_locations
KHR-GL45.enhanced_layouts.varying_structure_locations

Reviewed-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Andres Gomez <agomez at igalia.com>

---

 src/intel/compiler/brw_vec4.cpp | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index bbe4585e0c..73c40ad600 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2238,7 +2238,12 @@ vec4_visitor::lower_simd_width()
             if (linst->src[i].file == BAD_FILE)
                continue;
 
-            if (!is_uniform(linst->src[i]))
+            bool is_interleaved_attr =
+               linst->src[i].file == ATTR &&
+               stage_uses_interleaved_attributes(stage,
+                                                 prog_data->dispatch_mode);
+
+            if (!is_uniform(linst->src[i]) && !is_interleaved_attr)
                linst->src[i] = horiz_offset(linst->src[i], channel_offset);
          }