Mesa (master): radv: Make tess winding order a bit more intuitive.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 0c90ca7d37e479dbf1099321ec5cb53662b98744
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c90ca7d37e479dbf1099321ec5cb53662b98744

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Fri Oct  6 01:10:44 2017 +0200

radv: Make tess winding order a bit more intuitive.

Reviewed-by: Dave Airlie <airlied at redhat.com>

---

 src/amd/vulkan/radv_pipeline.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 95a00cb357..5da27935c2 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -266,7 +266,6 @@ radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
 	if (tcs_nir == NULL)
 		return;
 
-	tes_nir->info.tess.ccw = !tes_nir->info.tess.ccw;
 	nir_lower_tes_patch_vertices(tes_nir,
 				     tcs_nir->info.tess.tcs_vertices_out);
 
@@ -1555,9 +1554,9 @@ calculate_tess_state(struct radv_pipeline *pipeline,
 	else if (tes->info.tes.primitive_mode == GL_ISOLINES)
 		topology = V_028B6C_OUTPUT_LINE;
 	else if (ccw)
-		topology = V_028B6C_OUTPUT_TRIANGLE_CW;
-	else
 		topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
+	else
+		topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
 	if (pipeline->device->has_distributed_tess) {
 		if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||