Mesa (master): radv: set ALPHA_TO_MASK_ENABLE at blend state init

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 6732a8369a97ae37892302550a3cd7f041db5c66
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6732a8369a97ae37892302550a3cd7f041db5c66

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Oct  6 15:39:01 2017 +0200

radv: set ALPHA_TO_MASK_ENABLE at blend state init

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_pipeline.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5da27935c2..670b89c922 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -755,6 +755,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
 			       const struct radv_graphics_pipeline_create_info *extra)
 {
 	const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
+	const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
 	struct radv_blend_state *blend = &pipeline->graphics.blend;
 	unsigned mode = V_028808_CB_NORMAL;
 	uint32_t blend_enable = 0, blend_need_alpha = 0;
@@ -780,6 +781,10 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
 		S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
 		S_028B70_ALPHA_TO_MASK_OFFSET3(2);
 
+	if (vkms && vkms->alphaToCoverageEnable) {
+		blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
+	}
+
 	blend->cb_target_mask = 0;
 	for (i = 0; i < vkblend->attachmentCount; i++) {
 		const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
@@ -1041,7 +1046,6 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 				     const VkGraphicsPipelineCreateInfo *pCreateInfo)
 {
 	const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
-	struct radv_blend_state *blend = &pipeline->graphics.blend;
 	struct radv_multisample_state *ms = &pipeline->graphics.ms;
 	unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
 	int ps_iter_samples = 1;
@@ -1096,12 +1100,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 					S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
 	}
 
-	if (vkms) {
-		if (vkms->alphaToCoverageEnable)
-			blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
-
-		if (vkms->pSampleMask)
-			mask = vkms->pSampleMask[0] & 0xffff;
+	if (vkms && vkms->pSampleMask) {
+		mask = vkms->pSampleMask[0] & 0xffff;
 	}
 
 	ms->pa_sc_aa_mask[0] = mask | (mask << 16);