Mesa (master): radeonsi: add performance thresholds for CP DMA, decrease it for clears

[Marek Olšák]

Module: Mesa
Branch: master
Commit: ed7f27ded85991cbfed3e2a18f4dda0e3b35b31c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed7f27ded85991cbfed3e2a18f4dda0e3b35b31c

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Oct  7 20:50:16 2017 +0200

radeonsi: add performance thresholds for CP DMA, decrease it for clears

The first one isn't used yet.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_cp_dma.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 064f6c02cc..97adc27e7d 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -28,6 +28,12 @@
 #include "sid.h"
 #include "radeon/r600_cs.h"
 
+/* Recommended maximum sizes for optimal performance.
+ * Fall back to compute or SDMA if the size is greater.
+ */
+#define CP_DMA_COPY_PERF_THRESHOLD	(64 * 1024) /* copied from Vulkan */
+#define CP_DMA_CLEAR_PERF_THRESHOLD	(32 * 1024) /* guess (clear is much slower) */
+
 /* Set this if you want the ME to wait until CP DMA is done.
  * It should be set on the last CP DMA packet. */
 #define CP_DMA_SYNC		(1 << 0)
@@ -230,7 +236,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 	    (offset % 4 == 0) &&
 	    /* CP DMA is very slow. Always use SDMA for big clears. This
 	     * alone improves DeusEx:MD performance by 70%. */
-	    (size > 128 * 1024 ||
+	    (size > CP_DMA_CLEAR_PERF_THRESHOLD ||
 	     /* Buffers not used by the GFX IB yet will be cleared by SDMA.
 	      * This happens to move most buffer clears to SDMA, including
 	      * DCC and CMASK clears, because pipe->clear clears them before