Mesa (master): 40 new commits

[Eric Anholt]

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2687183a3493bec0dc9dd9ec13222da579ec51c2
Author: Eric Anholt <eric at anholt.net>
Date:   Tue Oct 10 11:19:23 2017 -0700

    broadcom/vc5: Fix handling of 5551 textures using the new gallium format.
    
    Like vc4, we have the alpha in the low bit.  Fixes a bunch of piglit
    texwrap failures.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4b515887469831468c1afb032e8c7431ccf4c6c
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 5 17:18:34 2017 -0700

    broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae9a56db6a73c6a5dfc237e30fdf8ad0186b884b
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 5 15:50:59 2017 -0700

    braodcom/vc5: Set up clear color for higher-bpp formats.
    
    Fixes arb_color_buffer_float-clear

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0561808c0442a10a47707cfc9f002e195316552
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 5 15:40:18 2017 -0700

    broadcom/vc5: Set up per-MRT clear colors.
    
    Fixes fbo-mrt-alphatest.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5208d2889e36831e27b7b943b6b1a9dcf4368009
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 5 15:19:49 2017 -0700

    broadcom/vc5: Fix blendfactor zero handling.
    
    I cut the line out to move it up to the top, when putting "0" in the
    switch made the compiler complain that that wasn't a valid enum.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffdba7fd4c47ba455eb7bb86b24275d2c0266737
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Oct 4 16:42:55 2017 -0700

    broadcom/vc5: Fix Rendering Mode Common Config's color store bitmask.
    
    This controls the RTs that get stored by the default resolved store, the
    same way that the extended resolved store packet has a RT bitmask.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b7de2a360ebb2d1cf7b3bbcc849026e5af47e41
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 17:21:23 2017 -0700

    broadcom/vc5: Add support for f32 render targets.
    
    The TLB write code is getting ugly and needs a refactoring (that will
    hopefully handle TLBU uniform coalescing as well).

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2e6e1bbc381ad6a7575e9940248362f8cb0adac
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 17:05:24 2017 -0700

    broadcom/vc5: Fix color masks for non-independent blending.
    
    This gets fbo-mrt-alphatest working except for the second RT's clear color.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=476db7e66b5c2b4cade87c7c8de4bea25ea9eb43
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 16:55:04 2017 -0700

    broadcom/vc5: Make the BCL's number of render targets setup match the RCL.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b4c00a7b2d65b97413ed344c016af88bc7eaaf2
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 16:54:09 2017 -0700

    braodcom/vc5: Fix tile size setup for MRTs.
    
    We need to divide the TLB in two for the 2nd color buffer, and again if
    the 3rd or 4th are present.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc25a83a7a0b71548d0d7b6f0021f73450ce0c6d
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 16:43:33 2017 -0700

    broadcom/vc5: Start hooking up multiple render targets support.
    
    We now emit as many TLB color writes as there are color buffers.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0ee7d6ba85c0695e276b61c8c8113552d8bde6c
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 14:09:56 2017 -0700

    broadcom/vc5: Add support for GL_EXT_provoking_vertex.
    
    The bit was missing from the spec, but it's there in the simulator.  Fixes
    the piglit clipflat test.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4133865d191c6a5377d63a2384e5844b1e0e14d
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 12:20:35 2017 -0700

    braodcom/vc5: Find the actual first TF output for our TF spec.
    
    This doesn't yet support PSIZ, but gets us at least some of TF working.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd94f6821e7bb3077df885375ef75741e7b804a0
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 13:02:32 2017 -0700

    broadcom/vc5: Fix translation of transform feedback's output_register field.
    
    It's a NIR driver_location, not a slot offset.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8bc9c71dfcfa4e1e43e899f6b67da45f26efc79
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 12:17:30 2017 -0700

    broadcom/vc5: Mark our primitives as needing TF processing.
    
    The TF enable state appears to stick around until the next TF enable
    packet is sent, so we only want to request TF when the shader is using it.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=28105560f778c4b7718349d3719cc96e15092f2b
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 12:05:30 2017 -0700

    broadcom/vc5: Fix setup of TF dword output count.
    
    I missed the "- 1" when reading the spec.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ac8a2a4ba0346ec2d23078ec0d6b10e74609274
Author: Eric Anholt <eric at anholt.net>
Date:   Mon Oct 2 11:41:57 2017 -0700

    broadcom/vc5: Fix up a comment from vc4 about the predraw texture setup.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec5af12b5d54f65ab119ce6f4eecd3a9fee5407d
Author: Eric Anholt <eric at anholt.net>
Date:   Sat Sep 30 16:48:44 2017 -0700

    broadcom/vc5: Flush the job when mapping a transform feedback buffer.
    
    We will want something fancier for reusing a TF output within the same
    frame, but we at least need this in order for piglit tests to work.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=361c5f28bdc6858618e9de85a340adce1b217e2c
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 14:02:05 2017 -0700

    broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.
    
    The interpolation qualifier, if specified, is supposed to take precedence
    over glShadeModel().

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0dfc4bd5f3711ac48de88aa51fc6f442eaa0b20
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 13:36:54 2017 -0700

    broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.
    
    The HW will halt when you hit a HALT packet, or when you hit the end
    address.  Tell CLIF if there's an end address is so that it can stop
    correctly.  (There was usually a 0 byte after the CL, so it would stop
    anyway).

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f3b8906979ba5f2c1876b4eb2c0b85314107511
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 11:41:31 2017 -0700

    broadcom/vc5: Fix depth and stencil clear values.
    
    I had misread the packet description: We always have a 32f depth, and a
    separate u8 stencil.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=be11251e3c0f4ef2ad57aa83dbb480bc2b95328a
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 11:47:50 2017 -0700

    broadcom/vc5: Add missing Z16 format.
    
    We can render to and sample from it just fine.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e20c82c55087344fb7caec4cc9df0a13489a2f2d
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 10:39:07 2017 -0700

    braodcom/vc5: Fix incorrect early Z writes in discard shaders.
    
    Fixes glsl-fs-discard-02.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=732a3a72cb8b5c78e95eee47572701b3f6055c19
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 10:37:02 2017 -0700

    broadcom/compiler: Set up passthrough Z when doing FS discards.
    
    In order to keep early-Z from writing early in a discard shader, you need
    to set the "modifies Z" bit in the shader state (which the new
    prog_data.discards will indicate).  Then, in the shader we do a TLB write
    to make Z passthrough happen (the QPU result is ignored, so we use a NULL
    source).

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c4fbab345c164284e62e5e2587382785ade1750
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 11:06:53 2017 -0700

    broadcom/compiler: Don't forget the discard state on TLB Z writes.
    
    We don't want to write Z for discarded fragments.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=84939552d00f758887a0a8572abec3465329a70b
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Sep 28 10:56:47 2017 -0700

    broadcom/compiler: Use defines instead of magic values in TLB write setup.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c25de31824a64873a9000ce10b90fcf493050a8a
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Sep 27 15:06:09 2017 -0700

    broadcom/vc5: Add proper support for base_vertex and base_instance.
    
    I had base_vertex hacked into the shader state setup like in vc4, but it's
    not correct for big offsets.  Using the proper packet is easier and
    hopefully means we can re-emit shader state setup less frequently.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e74a9e8def040d55d994c5233bca0ddcccda42d5
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Sep 27 15:05:14 2017 -0700

    broadcom/xml: Add the vc5 Base Vertex/Base Instance packet.
    
    This lets us do index_bias and ARB_base_instance.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=24c8bbbb758a1b6019829c6d12db9d64dd2007e9
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Sep 27 15:27:31 2017 -0700

    broadcom/vc5: Use supertiles and generic tile lists.
    
    This massively reduces the size of our RCL setup.  It also gets us closer
    to supporting multicore platforms.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b2cf771e6bcc7efc26b6fb48e979b93f5ce6e31
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Sep 27 14:51:05 2017 -0700

    broadcom/xml: Add a bunch more vc5 tile list management packets.
    
    We're going to need these for MSAA, and to use the generic per-tile list.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=efa329ab4f81b3cf7050418189f72f5547708bc1
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Sep 27 16:38:28 2017 -0700

    broadcom/xml: Remove vc5 base packet for tile bin/render mode config.
    
    These existed so I could unpack just the sub-id field to switch on in the
    old manual CLIF dumper.  The new codegen handles sub-id automatically, but
    only if these stub packets aren't there with an implicit sub-id=0.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=afb31a9e87b8a56ab1bf2db302386d873dd06d1e
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Sep 27 14:54:05 2017 -0700

    braodcom/xml: Fix a pasteo in vc5 store tile buffer general.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=45bb8f2957108056de10721d50259e2f8c5a4ddc
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Feb 2 16:24:13 2017 -0800

    broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.
    
    V3D 3.3 is a continuation of the 3D implementation in VC4 (v2.1 and v2.6).
    V3D 3.3 introduces an MMU (no more CMA allocations) and support for
    GLES3.1.  This driver is not currently conformant, though that will be a
    target as soon as possible.
    
    V3D 3.x parts use a new texture tiling layout common across many Broadcom
    graphics parts including and the HVS scanout engine.  It also massively
    changes the QPU instructions, introducing a common physical register file
    (no more A/B split) and half-float instructions, while removing the 4x8
    unorm instructions in favor of half-float for talking to fixed function
    interfaces.  Because so much has changed, vc5 is implemented in a separate
    gallium driver, using only the XML code-generation support from vc4.
    
    v2: Fix tile layout for 64bpp textures.  Fix texture swizzling for 32-bit
        returns.  Fix up a bit of MRT setup.  Sync the simulator to kernel
        behavior a bit more.  Improve uniform debugging code.  Rebase on
        QIR->VIR rename.  Move texture state mostly to the CSOs.  Improve
        cache flushing on the simulator.  Fix program deletion
        use-after-frees.
    
    Acked-by: Dave Airlie <airlied at gmail.com> (uabi plan)
    Acked-by: Daniel Vetter <daniel.vetter at ffwll.ch> (uabi plan)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ade416d02369cc0942d53ad3cce601d66344f9c3
Author: Eric Anholt <eric at anholt.net>
Date:   Fri Feb 3 10:24:14 2017 -0800

    broadcom: Add VC5 NIR compiler.
    
    This is a pretty straightforward fork of VC4's NIR compiler to VC5.  The
    condition codes, registers, and I/O have all changed, making the backend
    hard to share, though their heritage is still recognizable.
    
    v2: Move to src/broadcom/compiler to match intel's layout, rename more
        "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts
        with vc4, use new v3d_debug header, add compiler init/free functions,
        do texture swizzling in NIR to allow optimization.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f71364f29787d0f822474ed970c5f28bede49abb
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Feb 2 16:25:12 2017 -0800

    broadcom: Add vc5 CLIF dumping
    
    This will be usable with "VC5_DEBUG=cl" on the vc5 driver to stream a CLIF
    file (the Broadcom equivalent of i965's AUB) to stderr.  I haven't tested
    that this is actually usable with the internal CLIF-consuming tools, but
    is close enough as a baseline and is useful for visually inspecting the
    command stream.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=05c7d9715b8a419fd6fb952715ee8fde9401aacb
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Feb 2 16:15:18 2017 -0800

    broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.
    
    Unlike VC4, I've defined an unpacked instruction format with pack/unpack
    functions to convert to 64-bit encoded instructions.  This will let us
    incrementally put together our instructions and validate them in a more
    natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to.
    
    The pack/unpack unfortuantely are written by hand.  While I could define
    genxml for parts of it, there are many special cases (like operand order
    of commutative binops choosing which binop is being performed!) and it
    probably wouldn't come out much cleaner.
    
    The disasm unit test ensures that we have the same assembly format as
    Broadcom's internal tools, other than whitespace changes.
    
    v2: Fix automake variable redefinition complaints, add test to .gitignore

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=59257c35eb5ce4a58d6cff20ed24a8203b045af8
Author: Eric Anholt <eric at anholt.net>
Date:   Fri Sep 1 14:38:54 2017 -0700

    broadcom: Introduce a v3d_debug.h header for vc5 and broadcom Vulkan.
    
    Unlike vc4, where the compiler and gallium driver live together, for vc5
    the compiler will live up in the shared broadcom directory, and need
    access to the debug flags.  Define a set of debug flags and helpers there,
    so it can be shared between compiler, vc5, and vulkan.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae106592a60d5b35facfc6957919820393ec1d40
Author: Eric Anholt <eric at anholt.net>
Date:   Fri Aug 18 12:55:43 2017 -0700

    configure: Add the new "vc5" driver to the list, requiring a simulator.
    
    My intent is to develop the vc5 driver in-tree for some time to build the
    CL generation and shader compiler code, and keep out-of-tree patches for
    talking to an actual kernel driver until the kernel driver can be
    stabilized on the hardware.
    
    v2: Define a HAVE_BROADCOM_DRIVERS, like HAVE_INTEL or HAVE_AMD.
    
    Reviewed-by: Adam Jackson <ajax at redhat.com>
    Reviewed-by: Emil Velikov <emil.velikov at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c34295b1a3e2bd6ddf8a79bbe391aae1e98cd976
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Feb 22 16:53:18 2017 -0800

    nir: Move vc4's alpha test lowering to core NIR.
    
    I've been doing this inside of vc4, but vc5 wants it as well and it may be
    useful for other drivers (Intel has a related path for pre-gen6 with MRT,
    and freedreno had a TGSI path for it at one point).
    
    This required defining a common enum for the standard comparison
    functions, but other lowering passes are likely to also want that enum.
    
    v2: Add to meson.build as well.
    
    Acked-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e37b32f80c8ed95a3c3f49ba20d6155820c8bba8
Author: Eric Anholt <eric at anholt.net>
Date:   Tue Oct 10 11:41:29 2017 -0700

    mesa: Alphabetize GL_MESA_tile_raster_order in the extensions list.
    
    trivial, fixes make check.