Mesa (master): radv: set correct INDEX_TYPE for indexed indirect draws on GFX9

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: a4c08c8cd5257fd628ab829bec0a119076c8f641
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4c08c8cd5257fd628ab829bec0a119076c8f641

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Oct 13 18:01:56 2017 +0200

radv: set correct INDEX_TYPE for indexed indirect draws on GFX9

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_cmd_buffer.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 47495160ae..39dfffc376 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3058,8 +3058,14 @@ radv_cmd_draw_indexed_indirect_count(
 
 	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
 
-	radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
-	radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
+	if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+		radeon_set_uconfig_reg_idx(cmd_buffer->cs,
+					   R_03090C_VGT_INDEX_TYPE,
+					   2, cmd_buffer->state.index_type);
+	} else {
+		radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
+		radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
+	}
 
 	radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
 	radeon_emit(cmd_buffer->cs, index_va);