Mesa (master): radv/ac/nir: only emit tess factors to storage if tes reads them

[Dave Airlie]

Module: Mesa
Branch: master
Commit: da9c3cd3ee5494b43a8ab3f9a3fee95620d9d357
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=da9c3cd3ee5494b43a8ab3f9a3fee95620d9d357

Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Oct 23 06:23:29 2017 +1000

radv/ac/nir: only emit tess factors to storage if tes reads them

Otherwise we just need to write them to the tf ring.

this seems to improve the tessellation demo on Bonarie
~2190->~2230 fps

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied at redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 4 ++--
 src/amd/common/ac_nir_to_llvm.h | 1 +
 src/amd/vulkan/radv_pipeline.c  | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 83b49b535c..360ca81ca8 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6166,8 +6166,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
 					    stride - 4, byteoffset, tf_base,
 					    16 + tf_offset, 1, 0, true, false);
 
-	//TODO store to offchip for TES to read - only if TES reads them
-	if (1) {
+	//store to offchip for TES to read - only if TES reads them
+	if (ctx->options->key.tcs.tes_reads_tess_factors) {
 		LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
 		LLVMValueRef tf_inner_offset;
 		unsigned param_outer, param_inner;
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index eecc2cb8d4..9579aeeefe 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -55,6 +55,7 @@ struct ac_tcs_variant_key {
 	struct ac_vs_variant_key vs_key;
 	unsigned primitive_mode;
 	unsigned input_vertices;
+	uint32_t tes_reads_tess_factors:1;
 };
 
 struct ac_fs_variant_key {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f23afa42b7..669d9a4858 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1773,6 +1773,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 		if (keys)
 			keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
 
+		keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
 		nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
 	}