Mesa (master): radeonsi: don't set RB+ registers on GFX9 chips without RB+

[Marek Olšák]

Module: Mesa
Branch: master
Commit: f33e4482b391f8f69abdbd2831ed34c7b0e41138
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f33e4482b391f8f69abdbd2831ed34c7b0e41138

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Apr  7 11:53:26 2018 -0400

radeonsi: don't set RB+ registers on GFX9 chips without RB+

CLEAR_STATE initializes them properly.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

---

 src/gallium/drivers/radeonsi/si_state.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c4fb254c2e..2924a72f48 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -265,11 +265,6 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
 		radeon_emit(cs, sx_ps_downconvert);	/* R_028754_SX_PS_DOWNCONVERT */
 		radeon_emit(cs, sx_blend_opt_epsilon);	/* R_028758_SX_BLEND_OPT_EPSILON */
 		radeon_emit(cs, sx_blend_opt_control);	/* R_02875C_SX_BLEND_OPT_CONTROL */
-	} else if (sctx->screen->has_rbplus) {
-		radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
-		radeon_emit(cs, 0);	/* R_028754_SX_PS_DOWNCONVERT */
-		radeon_emit(cs, 0);	/* R_028758_SX_BLEND_OPT_EPSILON */
-		radeon_emit(cs, 0);	/* R_02875C_SX_BLEND_OPT_CONTROL */
 	}
 }
 
@@ -628,7 +623,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
 		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 	}
 
-	if (sctx->screen->has_rbplus) {
+	if (sctx->screen->rbplus_allowed) {
 		/* Disable RB+ blend optimizations for dual source blending.
 		 * Vulkan does this.
 		 */