Mesa (master): intel/compiler: Add scheduler deps for instructions that implicitly read g0

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0d5ce25c1ca23abc6d91538f4374a18509091060
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d5ce25c1ca23abc6d91538f4374a18509091060

Author: Ian Romanick <ian.d.romanick at intel.com>
Date:   Mon Apr 16 16:32:41 2018 -0700

intel/compiler: Add scheduler deps for instructions that implicitly read g0

Otherwise the scheduler can move the writes after the reads.

Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Cc: Clayton A Craft <clayton.a.craft at intel.com>
Cc: mesa-stable at lists.freedesktop.org

---

 src/intel/compiler/brw_ir_vec4.h                 | 25 ++++++++++++++++++++++++
 src/intel/compiler/brw_schedule_instructions.cpp |  3 +++
 2 files changed, 28 insertions(+)

diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
index 95c5119c6c..e401d8b4d1 100644
--- a/src/intel/compiler/brw_ir_vec4.h
+++ b/src/intel/compiler/brw_ir_vec4.h
@@ -334,6 +334,31 @@ public:
                                   opcode != BRW_OPCODE_IF &&
                                   opcode != BRW_OPCODE_WHILE));
    }
+
+   bool reads_g0_implicitly() const
+   {
+      switch (opcode) {
+      case SHADER_OPCODE_TEX:
+      case SHADER_OPCODE_TXL:
+      case SHADER_OPCODE_TXD:
+      case SHADER_OPCODE_TXF:
+      case SHADER_OPCODE_TXF_CMS_W:
+      case SHADER_OPCODE_TXF_CMS:
+      case SHADER_OPCODE_TXF_MCS:
+      case SHADER_OPCODE_TXS:
+      case SHADER_OPCODE_TG4:
+      case SHADER_OPCODE_TG4_OFFSET:
+      case SHADER_OPCODE_SAMPLEINFO:
+      case VS_OPCODE_PULL_CONSTANT_LOAD:
+      case GS_OPCODE_SET_PRIMITIVE_ID:
+      case GS_OPCODE_GET_INSTANCE_ID:
+      case SHADER_OPCODE_GEN4_SCRATCH_READ:
+      case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+         return true;
+      default:
+         return false;
+      }
+   }
 };
 
 /**
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index fa85045de7..f817142a8b 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -1267,6 +1267,9 @@ vec4_instruction_scheduler::calculate_deps()
          }
       }
 
+      if (inst->reads_g0_implicitly())
+         add_dep(last_fixed_grf_write, n);
+
       if (!inst->is_send_from_grf()) {
          for (int i = 0; i < inst->mlen; i++) {
             /* It looks like the MRF regs are released in the send