Mesa (master): mesa: Revert INTEL_fragment_shader_ordering support

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Mon Dec 3 23:37:49 UTC 2018


Module: Mesa
Branch: master
Commit: 017199d2d2e4c57015bc60edfcc656062c3a7472
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=017199d2d2e4c57015bc60edfcc656062c3a7472

Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Nov 29 15:46:18 2018 -0800

mesa: Revert INTEL_fragment_shader_ordering support

This extension is not properly tested (testing for
GL_ARB_fragment_shader_interlock is not sufficient), and since this was
noted in review on August 28th no tests have been sent.

Revert "i965: Add INTEL_fragment_shader_ordering support."
Revert "mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering"

This reverts commit 03ecec9ed2099f6e2b62994b33dc948dc731e7b8.
This reverts commit 119435c8778dd26cb7c8bcde9f04b3982239fe60.

Cc: mesa-stable at lists.freedesktop.org
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Eric Anholt <eric at anholt.net>

---

 docs/relnotes/18.3.0.html                    |  1 -
 src/compiler/glsl/builtin_functions.cpp      | 17 -----------------
 src/compiler/glsl/glsl_parser_extras.cpp     |  1 -
 src/compiler/glsl/glsl_parser_extras.h       |  2 --
 src/compiler/glsl/glsl_to_nir.cpp            |  6 ------
 src/compiler/glsl/ir.h                       |  1 -
 src/compiler/nir/nir_intrinsics.py           |  1 -
 src/intel/compiler/brw_fs_nir.cpp            |  1 -
 src/mesa/drivers/dri/i965/intel_extensions.c |  1 -
 src/mesa/main/extensions_table.h             |  1 -
 src/mesa/main/mtypes.h                       |  1 -
 11 files changed, 33 deletions(-)

diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index 8af225a61e..aa92439191 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -61,7 +61,6 @@ Note: some of the new features are only available with certain drivers.
 <li>GL_EXT_vertex_attrib_64bit on i965, nvc0, radeonsi.</li>
 <li>GL_EXT_window_rectangles on radeonsi.</li>
 <li>GL_KHR_texture_compression_astc_sliced_3d on radeonsi.</li>
-<li>GL_INTEL_fragment_shader_ordering on i965.</li>
 <li>GL_NV_fragment_shader_interlock on i965.</li>
 <li>EGL_EXT_device_base for all drivers.</li>
 <li>EGL_EXT_device_drm for all drivers.</li>
diff --git a/src/compiler/glsl/builtin_functions.cpp b/src/compiler/glsl/builtin_functions.cpp
index 5650365d1d..b601880686 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -526,12 +526,6 @@ supports_nv_fragment_shader_interlock(const _mesa_glsl_parse_state *state)
 }
 
 static bool
-supports_intel_fragment_shader_ordering(const _mesa_glsl_parse_state *state)
-{
-   return state->INTEL_fragment_shader_ordering_enable;
-}
-
-static bool
 shader_clock(const _mesa_glsl_parse_state *state)
 {
    return state->ARB_shader_clock_enable;
@@ -1311,11 +1305,6 @@ builtin_builder::create_intrinsics()
                    supports_arb_fragment_shader_interlock,
                    ir_intrinsic_end_invocation_interlock), NULL);
 
-   add_function("__intrinsic_begin_fragment_shader_ordering",
-                _invocation_interlock_intrinsic(
-                   supports_intel_fragment_shader_ordering,
-                   ir_intrinsic_begin_fragment_shader_ordering), NULL);
-
    add_function("__intrinsic_shader_clock",
                 _shader_clock_intrinsic(shader_clock,
                                         glsl_type::uvec2_type),
@@ -3430,12 +3419,6 @@ builtin_builder::create_builtins()
                    supports_nv_fragment_shader_interlock),
                 NULL);
 
-   add_function("beginFragmentShaderOrderingINTEL",
-                _invocation_interlock(
-                   "__intrinsic_begin_fragment_shader_ordering",
-                   supports_intel_fragment_shader_ordering),
-                NULL);
-
    add_function("anyInvocationARB",
                 _vote("__intrinsic_vote_any", vote),
                 NULL);
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp
index 21ed34d79d..f9178d8c10 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -730,7 +730,6 @@ static const _mesa_glsl_extension _mesa_glsl_supported_extensions[] = {
    EXT_AEP(EXT_texture_buffer),
    EXT_AEP(EXT_texture_cube_map_array),
    EXT(INTEL_conservative_rasterization),
-   EXT(INTEL_fragment_shader_ordering),
    EXT(INTEL_shader_atomic_float_minmax),
    EXT(MESA_shader_integer_functions),
    EXT(NV_fragment_shader_interlock),
diff --git a/src/compiler/glsl/glsl_parser_extras.h b/src/compiler/glsl/glsl_parser_extras.h
index da8b2fa3ab..7ceee7469d 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -834,8 +834,6 @@ struct _mesa_glsl_parse_state {
    bool EXT_texture_cube_map_array_warn;
    bool INTEL_conservative_rasterization_enable;
    bool INTEL_conservative_rasterization_warn;
-   bool INTEL_fragment_shader_ordering_enable;
-   bool INTEL_fragment_shader_ordering_warn;
    bool INTEL_shader_atomic_float_minmax_enable;
    bool INTEL_shader_atomic_float_minmax_warn;
    bool MESA_shader_integer_functions_enable;
diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp
index 55628dd2cc..5e70d23055 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -747,9 +747,6 @@ nir_visitor::visit(ir_call *ir)
       case ir_intrinsic_end_invocation_interlock:
          op = nir_intrinsic_end_invocation_interlock;
          break;
-      case ir_intrinsic_begin_fragment_shader_ordering:
-         op = nir_intrinsic_begin_fragment_shader_ordering;
-         break;
       case ir_intrinsic_group_memory_barrier:
          op = nir_intrinsic_group_memory_barrier;
          break;
@@ -988,9 +985,6 @@ nir_visitor::visit(ir_call *ir)
       case nir_intrinsic_end_invocation_interlock:
          nir_builder_instr_insert(&b, &instr->instr);
          break;
-      case nir_intrinsic_begin_fragment_shader_ordering:
-         nir_builder_instr_insert(&b, &instr->instr);
-         break;
       case nir_intrinsic_store_ssbo: {
          exec_node *param = ir->actual_parameters.get_head();
          ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
diff --git a/src/compiler/glsl/ir.h b/src/compiler/glsl/ir.h
index f478b29a6b..d05d1998a5 100644
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -1122,7 +1122,6 @@ enum ir_intrinsic_id {
    ir_intrinsic_memory_barrier_shared,
    ir_intrinsic_begin_invocation_interlock,
    ir_intrinsic_end_invocation_interlock,
-   ir_intrinsic_begin_fragment_shader_ordering,
 
    ir_intrinsic_vote_all,
    ir_intrinsic_vote_any,
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 735db43d16..6ea6ad1198 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -202,7 +202,6 @@ barrier("memory_barrier_image")
 barrier("memory_barrier_shared")
 barrier("begin_invocation_interlock")
 barrier("end_invocation_interlock")
-barrier("begin_fragment_shader_ordering")
 
 # A conditional discard, with a single boolean source.
 intrinsic("discard_if", src_comp=[1])
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 6eb68794f5..1ebb4c3fbe 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4567,7 +4567,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
       break;
    }
 
-   case nir_intrinsic_begin_fragment_shader_ordering:
    case nir_intrinsic_begin_invocation_interlock: {
       const fs_builder ubld = bld.group(8, 0);
       const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 6ec6248a70..c1e92e586e 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -248,7 +248,6 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.OES_primitive_bounding_box = true;
       ctx->Extensions.OES_texture_buffer = true;
       ctx->Extensions.ARB_fragment_shader_interlock = true;
-      ctx->Extensions.INTEL_fragment_shader_ordering = true;
 
       if (can_do_pipelined_register_writes(brw->screen)) {
          ctx->Extensions.ARB_draw_indirect = true;
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index dd846d7bc5..5c03bb0d9d 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -319,7 +319,6 @@ EXT(IBM_texture_mirrored_repeat             , dummy_true
 EXT(INGR_blend_func_separate                , EXT_blend_func_separate                , GLL,  x ,  x ,  x , 1999)
 
 EXT(INTEL_conservative_rasterization        , INTEL_conservative_rasterization       ,  x , GLC,  x ,  31, 2013)
-EXT(INTEL_fragment_shader_ordering          , INTEL_fragment_shader_ordering         , GLL, GLC,  x ,  x , 2013)
 EXT(INTEL_performance_query                 , INTEL_performance_query                , GLL, GLC,  x , ES2, 2013)
 EXT(INTEL_shader_atomic_float_minmax        , INTEL_shader_atomic_float_minmax       , GLL, GLC,  x ,  x , 2018)
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 157d45bc0b..411d30602f 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4307,7 +4307,6 @@ struct gl_extensions
    GLboolean ATI_fragment_shader;
    GLboolean GREMEDY_string_marker;
    GLboolean INTEL_conservative_rasterization;
-   GLboolean INTEL_fragment_shader_ordering;
    GLboolean INTEL_performance_query;
    GLboolean INTEL_shader_atomic_float_minmax;
    GLboolean KHR_blend_equation_advanced;




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