Mesa (master): 26 new commits
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Wed Dec 19 11:04:54 UTC 2018
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d73a25f2c0ae64e208a1511c785e35f5d74f4cd6
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Sep 20 10:21:26 2018 +0200
radeonsi: const-ify the si_query_ops
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c85b0dea0aebd10968748e14623e5460635a17af
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Tue Sep 18 22:29:41 2018 +0200
radeonsi: split perfcounter queries from si_query_hw
Remove a level of indirection to make the code more explicit -- should
make it easier to follow what's going on.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0f0d3675d462aad4ca30e4383a3530d46e6e85d
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Tue Sep 18 15:52:17 2018 +0200
radeonsi: factor si_query_buffer logic out of si_query_hw
This is a move towards using composition instead of inheritance for
different query types.
This change weakens out-of-memory error reporting somewhat, though this
should be acceptable since we didn't consistently report such errors in
the first place.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fc6e573dddbaaeac517bb8b03c1484a50943cd9
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Tue Sep 18 14:43:09 2018 +0200
radeonsi: move query suspend logic into the top-level si_query struct
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2b9329f17eaf94c0cb6cc9f9bad907500fedeba
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Tue Sep 18 14:16:10 2018 +0200
radeonsi: move remaining perfcounter code into si_perfcounter.c
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dd289d9e4a141a5af786530a010ac0aecdae8b4
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Fri Sep 21 17:19:34 2018 +0200
radeonsi: track constant buffer bind history in si_pipe_set_constant_buffer
Other callers of si_set_constant_buffer don't need it.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=829d4179145e9e365b8270080510a394a547e92e
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Sep 20 10:47:03 2018 +0200
radeonsi: use si_set_rw_shader_buffer for setting streamout buffers
Reduce the number of places that encode buffer descriptors.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce785f5ffd7dbed14a3909164e55a975a023ee97
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Fri Sep 21 17:35:56 2018 +0200
radeonsi: add an si_set_rw_shader_buffer convenience function
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=556c4c42b76c5bb399d0f3e6cfc2b9f58d4363e4
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Sun Sep 16 15:56:13 2018 +0200
radeonsi: avoid using hard-coded SI_NUM_RW_BUFFERS
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e49d723177a02d8727f44c4d222f774f818d65f
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Fri Aug 31 19:51:50 2018 +0200
radeonsi: show the fixed function TCS in debug dumps
This is rather important for merged VS/TCS as LSHS shaders...
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e67e79de4985b20aa0dfa400fa3e6564326a66e
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Aug 30 17:11:23 2018 +0200
radeonsi: const-ify si_set_tesseval_regs
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c841a1b1e1ab13e56590a08847733326c792f6f
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Jul 2 18:41:06 2018 +0200
radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purpose
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d58dcc3cff2f491f7c57c5c5c9d4b28e7f842b2
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Fri Sep 21 18:05:19 2018 +0200
radeonsi: don't set RAW_WAIT for CP DMA clears
There is never a read-after-write hazard because the command doesn't read.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23af72af25b26e290a903611e1aa5b5d1cb10b40
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Fri Jun 29 00:08:26 2018 +0200
radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when available
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f18b2ac0db4fe3cd3a49d04c70869e81040291ff
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Nov 16 12:14:51 2017 +0100
radeonsi: add si_init_draw_functions and make some functions static
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=555cb668cc909d5e05a81297aa775b4c346a1832
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Sun Nov 19 17:29:31 2017 +0100
radeonsi: extract declare_vs_blit_inputs
Prepare for some later refactoring.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec22dd34c88f8b24a1b4f5b25f4de2aa89f0cad4
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Sat Nov 18 23:23:04 2017 +0100
radeonsi: move SI_FORCE_FAMILY functionality to winsys
This helps some debugging cases by initializing addrlib with
slightly more appropriate settings.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ef263d62f450b5a064b7acd2252a3c7fe6838d0
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Nov 29 18:34:01 2018 +0100
ac/surface: 3D and cube surfaces are never displayable
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8efaffa8932d113e5d0c753286d368ae053132f1
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Sep 20 19:09:50 2018 +0200
amd/common: add i1 special case to ac_build_{inclusive,exclusive}_scan
Allow for a unified but efficient treatment of adding a bitmask over a
wave or an entire threadgroup.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=300876a9a7f849a2b165360e19ec1708a342b68c
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Wed May 23 22:09:27 2018 +0200
amd/common: scan/reduce across waves of a workgroup
Order-aware scan/reduce can trade-off LDS traffic for external atomics
memory traffic in producer/consumer compute shaders.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3963402fd343dd4cd7bef0f6b64e51e029798944
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Wed May 23 22:04:20 2018 +0200
amd/common: add ac_build_ifcc
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c77f26ccc16f5e0fe58ef886d22efb0345a9ba5
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Nov 29 19:00:15 2018 +0100
amd/common: whitespace fixes
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76c5ad1995cf48c3a5281fc4e8b6e3de58880ed7
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Sun Nov 19 12:59:45 2017 +0100
amd/sid_tables: add additional python3 compatibility imports
This happened to bite me while doing some experiments.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f0322b16a3fc698496d836c8b7a7152d8a1b75c
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Nov 29 13:48:03 2018 +0100
r600: remove redundant semicolon
Reviewed-By: Gert Wollny <gert.wollny at collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7230cb8f2b9cfed6510db4d44a9ee20dbb92c8b0
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Aug 27 15:24:07 2018 +0200
ddebug: always flush when requested, even when hang detection is disabled
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=539fdc49f1ef02f5a40c486fa940b3bfacb44a48
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon May 28 17:30:25 2018 +0200
ddebug: simplify watchdog loop and fix crash in the no-timeout case
The following race condition could occur in the no-timeout case:
API thread Gallium thread Watchdog
---------- -------------- --------
dd_before_draw
u_threaded_context draw
dd_after_draw
add to dctx->records
signal watchdog
dump & destroy record
execute draw
dd_after_draw_async
use-after-free!
Alternatively, the same scenario would assert in a debug build when
destroying the record because record->driver_finished has not signaled.
Fix this and simplify the logic at the same time by
- handing the record pointers off to the watchdog thread *before* each
draw call and
- waiting on the driver_finished fence in the watchdog thread
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
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