Mesa (master): r600: fix texture gather swizzling.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 2a891ed19065dac89e8639800d3c63274d19a97a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a891ed19065dac89e8639800d3c63274d19a97a

Author: Dave Airlie <airlied at redhat.com>
Date:   Thu Feb  8 16:19:28 2018 +1000

r600: fix texture gather swizzling.

This fixes:
KHR-GL45.texture_gather.swizzle
on cayman and redwood.

Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 358fc4c33d..903a663026 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -7976,15 +7976,15 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		tex.inst_mod = texture_component_select;
 
 		if (ctx->bc->chip_class == CAYMAN) {
-		/* GATHER4 result order is different from TGSI TG4 */
-			tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
-			tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
-			tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
+			tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+			tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+			tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
 			tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
 		} else {
-			tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
-			tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
-			tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+			/* GATHER4 result order is different from TGSI TG4 */
+			tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
+			tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
+			tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
 			tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
 		}
 	}