Mesa (master): 23 new commits

Fri Feb 9 00:35:50 UTC 2018

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f20cf166ed434092242dba05a09f682df3028d8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jan 19 15:14:37 2018 -0800

    intel/blorp: Use isl_aux_op instead of blorp_hiz_op
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e941a05283b6873d2501f17944e545f6c76166f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jan 19 15:02:07 2018 -0800

    intel/blorp: Use isl_aux_op instead of blorp_fast_clear_op
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1810f965c8e490eac164732883d5242748b5911f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jan 19 12:07:12 2018 -0800

    anv: Allow fast-clearing the first slice of a multi-slice image
    
    Now that we're tracking aux properly per-slice, we can enable this for
    applications which actually care.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=de3be6180169f95b781308398b31fbdd3db319e1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Nov 21 08:46:25 2017 -0800

    anv/cmd_buffer: Rework aux tracking
    
    This commit completely reworks aux tracking.  This includes a number of
    somewhat distinct changes:
    
     1) Since we are no longer fast-clearing multiple slices, we only need
        to track one fast clear color and one fast clear type.
    
     2) We store two bits for fast clear instead of one to let us
        distinguish between zero and non-zero fast clear colors.  This is
        needed so that we can do full resolves when transitioning to
        PRESENT_SRC_KHR with gen9 CCS images where we allow zero clear
        values in all sorts of places we wouldn't normally.
    
     3) We now track compression state as a boolean separate from fast clear
        type and this is tracked on a per-slice granularity.
    
    The previous scheme had some issues when it came to individual slices of
    a multi-LOD images.  In particular, we only tracked "needs resolve"
    per-LOD but you could do a vkCmdPipelineBarrier that would only resolve
    a portion of the image and would set "needs resolve" to false anyway.
    Also, any transition from an undefined layout would reset the clear
    color for the entire LOD regardless of whether or not there was some
    clear color on some other slice.
    
    As far as full/partial resolves go, he assumptions of the previous
    scheme held because the one case where we do need a full resolve when
    CCS_E is enabled is for window-system images.  Since we only ever
    allowed X-tiled window-system images, CCS was entirely disabled on gen9+
    and we never got CCS_E.  With the advent of Y-tiled window-system
    buffers, we now need to properly support doing a full resolve of images
    marked CCS_E.
    
    v2 (Jason Ekstrand):
     - Fix an bug in the compressed flag offset calculation
     - Treat 3D images as multi-slice for the purposes of resolve tracking
    
    v3 (Jason Ekstrand):
     - Set the compressed flag whenever we fast-clear
     - Simplify the resolve predicate computation logic
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cbfcb205ef777cb6e17ebca3ff658f9f2cb915f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jan 18 16:08:31 2018 -0800

    anv/cmd_buffer: Move the mi_alu helper higher up
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e69045c4d37f5ddd56b284b225a7f11a374381c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jan 18 09:17:17 2018 -0800

    anv/image: Simplify some verbose commennts
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0523f70ef4e3788a4510581c641dcea51640417
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 27 18:09:48 2017 -0800

    anv: Use blorp_ccs_ambiguate instead of fast-clears
    
    Even though the blorp pass looks a bit on the sketchy side, the end
    result in the Vulkan driver is very nice.  Instead of having this weird
    case where you do a fast clear and then maybe have to resolve, we just
    do the ambiguate and are done with it.  The ambiguate does exactly what
    we want of setting all the CCS values to 0 which puts it into the
    pass-through state.
    
    This should also improve performance a bit in certain cases.  For
    instance, if we did a transition from UNDEFINED to GENERAL for a surface
    that doesn't have CCS enabled all the time, we would end up doing a
    fast-clear and then a full resolve which ends up touching every byte in
    the main surface as well as the CCS.  With the ambiguate pass, that
    transition only touches the CCS.
    
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=84fd2ebfbcd743840a173a2e8b4268991e0fcc78
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 27 18:07:57 2017 -0800

    anv/cmd_buffer: Re-arrange the logic around UNDEFINED fast-clears
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ef8c4b2f53e00701375597aaaef9fc9617d7b4d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 27 18:06:47 2017 -0800

    anv/cmd_buffer: Pull the undefined layout condition into the if
    
    Now that this isn't a multi-case if and it's just the one case, it's a
    bit clearer if the condition is just part of the if instead of being
    pulled out into a boolean variable.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=857b5b5a7f7741b5433c59814c66d0612c05ae7d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 17 20:33:21 2017 -0700

    intel/blorp: Add a CCS ambiguation pass
    
    This pass performs an "ambiguate" operation on a CCS-compressed surface
    by manually writing zeros into the CCS.  On gen8+, ISL gives us a fairly
    detailed notion of how the CCS is laid out so this is fairly simple to
    do.  On gen7, the CCS tiling is quite crazy but that isn't an issue
    because we can only do CCS on single-slice images so we can just blast
    over the entire CCS buffer if we want to.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=13b621d6fd30b7337844ff53cc8b166d07154a82
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Jan 17 21:31:09 2018 -0800

    anv: Only fast clear single-slice images
    
    The current strategy we use for managing resolves has an issues where we
    track clear colors and the need for resolves per-LOD but we still allow
    resolves of only a subset of the slices in any given LOD and doing so
    sets the "needs resolve" flag for that LOD to false while leaving the
    remaining layers unresolved.  This patch is only the first step and does
    not, by itself fix anything.  However, it's fairly self-contained and
    splitting it out means any performance regressions should bisect to this
    nice obvious commit rather than to the giant "rework aux tracking"
    commit.
    
    Nanley and I did some testing and none of the applications we tested
    even tried to fast-clear anything other than the first slice of an
    image.  The test was done by adding a printf right before we call
    blorp_fast_clear if we were every going to touch any slice other than
    the first with a fast-clear.  Due to the way the original code was
    structured, this would not have included applications which only cleared
    a subset of layers.  The applications tested were:
    
     * All Sascha Willems demos
     * Aztec Ruins
     * Dota 2
     * The Talos Principle
     * Mad Max
     * Warhammer 40,000: Dawn of War III
     * Serious Sam Fusion 2017: BFE
    
    While not the full list of shipping applications, it's a pretty good
    spread and covers most of the engines we've seen running on our driver.
    If this is ever shown to be a performance problem in the future, we can
    reconsider our strategy.
    
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=571ed588ac5385a1c145d210a1c7b334e04c40ce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 27 08:35:12 2017 -0800

    anv/cmd_buffer: Add a mark_image_written helper
    
    Currently, this helper does nothing but we call it every place where an
    image is written through the render pipeline.  This will allow us to
    properly mark the aux state so that we can handle resolves correctly.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9876d6f0efd0484e7f0b2b69b91763bdfb9b19a3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jan 19 09:12:17 2018 -0800

    anv/blorp: Add src/dst_level helper variables in CmdCopyImage
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c180c2c868f2fccde224a959b5dcba4486cc4c60
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 27 08:29:34 2017 -0800

    anv/cmd_buffer: Add an anv_genX_call macro
    
    This is copied and pasted from the similar macro we added to ISL.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab7543b13d87577ccb5ca3b4693c1fa3e363bde0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 20 10:12:37 2017 -0800

    anv/cmd_buffer: Generalize transition_color_buffer
    
    This moves it to being based on layout_to_aux_usage instead of being
    hard-coded based on bits of a priori knowledge of how transitions
    interact with layouts.  This conceptually simplifies things because
    we're now using layout_to_aux_usage and layout_supports_fast_clear to
    make resolve decisions so changes to those functions will do what one
    expects.
    
    There is a potential bug with window system integration on gen9+ where
    we wouldn't do a resolve when transitioning to the PRESENT_SRC layout
    because we just assume that everything that handles CCS_E can handle it
    all the time.  When handing a CCS_E image off to the window system, we
    may need to do a full resolve if the window system does not support the
    CCS_E modifier.  The only reason why this hasn't been a problem yet is
    because we don't support modifiers in Vulkan WSI and so we always get X
    tiling which implies no CCS on gen9+.  This patch doesn't actually fix
    that bug yet but it takes us the first step in that direction by making
    us actually pick the correct resolve op.  In order to handle all of the
    cases, we need more detailed aux tracking.
    
    v2 (Jason Ekstrand):
     - Make a few more things const
     - Use the anv_fast_clear_support enum
    
    v3 (Jason Ekstrand):
     - Move an assert and add a better comment
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=151771b390fbfc26bb42bf26c2b55ca23051f62c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 20 10:05:54 2017 -0800

    anv/cmd_buffer: Recurse in transition_color_buffer instead of falling through
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bea7373c9284556571fe9c54fd0bd1d0887da032
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 20 12:05:20 2017 -0800

    anv/image: Support color aspects in layout_to_aux_usage
    
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b09464db42f31be768cb79ef623ea2ed9398c6a9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 20 09:48:39 2017 -0800

    anv/image: Add a helper for determining when fast clears are supported
    
    v2 (Jason Ekstrand):
     - Return an enum instead of a boolean
    
    v3 (Jason Ekstrand):
     - Return ANV_FAST_CLEAR_NONE instead of false (Topi)
     - Rename ANV_FAST_CLEAR_ANY to ANV_FAST_CLEAR_DEFAULT_VALUE
     - Add documentation for the enum values
    
    v4 (Jason Ekstrand):
     - Remove a dead comment
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f7eee6bc15f93d859ba134e9264354c3e79d05d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 20 09:47:47 2017 -0800

    anv/image: Update a comment
    
    This got lost in all of the aspect vs. plane rebasing of YCBCR.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c38ab8f0745ebbdf442bd865affd613491f6f91
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Nov 21 10:20:57 2017 -0800

    anv/blorp: Rework HiZ ops to look like MCS and CCS
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d473e26f25c6be18066eda9f4bf8365eb83d7ef
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Nov 21 12:10:30 2017 -0800

    anv/blorp: Support ISL_AUX_USAGE_HIZ in surf_for_anv_image
    
    If the function gets passed ANV_AUX_USAGE_DEFAULT, it still has the old
    behavior of setting ISL_AUX_USAGE_NONE for depth/stencil which is what
    we want for blits/copies.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=42f1668a54da40d96ddd92e52b958f376fbfe484
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Nov 21 09:56:41 2017 -0800

    anv/blorp: Rework image clear/resolve helpers
    
    This replaces image_fast_clear and ccs_resolve with two new helpers that
    simply perform an isl_aux_op whatever that may be on CCS or MCS.  This
    is a bit cleaner as it separates performing the aux operation from which
    blorp helper we have to call to do it.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=482c24783e3ddd55bc2d0cf4fe52e52cfa8f86b6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Nov 21 09:16:18 2017 -0800

    intel/isl: Codify AUX operations in an enum
    
    Right now, we have different entrypoints and enums in blorp for these
    different operations.  This provides us a central enum which we can
    begin to transition to.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>