Mesa (master): 31 new commits

Rob Clark robclark at kemper.freedesktop.org
Sun Feb 11 17:39:29 UTC 2018 

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=831fb29252859c8aaf2bc1c2573a83f30d664204
Author: Rob Clark <robdclark at gmail.com>
Date:   Sat Feb 10 14:12:11 2018 -0500

    freedreno: small fix for flushing dependent batches
    
    Flush a resource's previous write_batch synchronously.  Because a
    resource's associated batches are not updated until after the flush
    thread submits rendering to the kernel, this was causing a bit of
    confusion in the following loop.  This fixes a bug that appeared with
    recent stk.
    
    Perhaps we need to re-work things a bit to clear out dependent patches
    in the ctx's thread and use a fence to deal with the period between
    when a flush is queued and when it is submitted to the kernel.  But
    this will do until time permits a larger refactor.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c57ed8e01cb40ef9a422346c3d304c1a3cc1f418
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Feb 5 08:45:29 2018 -0500

    freedreno/ir3: intra-block scheduling
    
    Because of loops, we can't schedule all of a block's predecessors first.
    Instead just assume that the result consumed in a block was written far
    enough away in all paths into a block.  And do an intra-block scheduling
    pass to figure out if there are any cases where we need to insert extra
    nop's.  This works out better than always assuming the worst case (ie.
    that a value live into a block was written in the last instruction in
    the predecessor block).
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a2099a875568f2d979f0030aa6291ed88366046
Author: Rob Clark <robdclark at gmail.com>
Date:   Sun Feb 4 12:52:24 2018 -0500

    freedreno/ir3: "boost" the depth of if/else condition
    
    Account for the move to predicate register, to try to avoid needing to
    insert extra NOPs later.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffb00f6841768e842a010f895b52314e1eeb5828
Author: Rob Clark <robdclark at gmail.com>
Date:   Sun Feb 4 12:42:19 2018 -0500

    freedreno/ir3: account for arrays in delayslot calc
    
    Normally false-deps are not something to consider, since they mostly
    exist for delay-slot related reasons:
    
     * barriers
     * ordering writes after read
     * SSBO/image access ordering
    
    The exception is a false-dependency on an array store.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f54d2b4f10481913528b4ef3d68a99b59104f053
Author: Rob Clark <robdclark at gmail.com>
Date:   Thu Feb 1 09:08:39 2018 -0500

    freedreno/ir3: more clever legalize algorithm
    
    Previously we didn't handle flow control in legalize, and instead just
    set (ss)(sy) on the first instruction in every block.  Which isn't very
    clever.
    
    Instead, consider output state of all predecessor blocks, so we only
    set a sync bit if needed for any possible path leading into a block.
    Because of loops, we can't require that all successor blocks are
    legalized before a given block, so instead run in a loop until results
    converge.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=015afb6a3840af279e12e47833d7acb66fe71143
Author: Rob Clark <robdclark at gmail.com>
Date:   Wed Jan 31 12:58:05 2018 -0500

    freedreno/ir3: track block predecessors
    
    Useful in the following patches.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=76440fcca9150645c5d7a5396f902f42fd565937
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:59:55 2018 -0500

    freedreno/ir3: clean up dangling false-dep's
    
    Maybe there is a better way for this..  where it comes useful is "array"
    loads, which end up as a false-dep for a later array store.
    
    If all the uses of an array load are CP'd into their consumer, it still
    leaves the dangling array load, leading to funny things like:
    
      mov.u32u32 r5.y, r0.y
      mov.u32u32 r5.y, r0.z
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aea223741fa008c704e8bc66fe00bde05d51b2c7
Author: Rob Clark <robdclark at gmail.com>
Date:   Tue Jan 30 12:18:13 2018 -0500

    freedreno/ir3: handle IMMED for mad 2nd src special case
    
    Consider also immediates for swapping the first two srcs, because they
    can be lowered to constant.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=242a8a1957c631e557c6148b5d024dc647b493ed
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 16:22:26 2018 -0500

    freedreno/ir3: remove ir3 phi instruction
    
    Now that we convert phi webs to ssa, we can drop all this.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7b569d60c72726f0f630acab0a1ce160321de83
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 16:09:44 2018 -0500

    freedreno/ir3: remove lower_if_else pass
    
    Now that it is unused.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=268ab05484379a35a54c14de9c111a52d338b2fd
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 14:53:13 2018 -0500

    freedreno/ir3: add experimental GCM pass
    
    Generally seems to do worse on instruction count and register usage,
    according to shader-db.  But shader-db also doesn't do a very good job
    of weighting loop bodies, so that might not be totally valid.
    
    So add an env variable to enable GCM pass for easier experimentation.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c15c53d91dff8ec0573421e234940c99f8a54cb
Author: Rob Clark <robdclark at gmail.com>
Date:   Fri Jan 26 10:43:48 2018 -0500

    freedreno/ir3: change opt passes
    
    There are more useful nir passes added since initial conversion to nir.
    But ir3 was never updated to use them.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec8bc54ad2ce4e05ff8e3679672a616b1984be80
Author: Rob Clark <robdclark at gmail.com>
Date:   Fri Jan 19 16:13:09 2018 -0500

    freedreno/ir3: use peephole select pass
    
    Agressively lowering all if/else to selects in some extreme cases
    results in much higher register pressure.  Using peephole select instead
    with a modest threshold speeds up alu2 4x!
    
    16 seems like a good limit, low enough to help alu2 but not too low that
    it penalizes everything else.  With a bit better scheduling of the
    instruction that moves a value into a predicate register, we might be
    able to lower this limit a bit more in the future, but since we need 6
    cycles from the move to predicate register to predicated branch, that
    puts some sort of lower bound on how far we can lower this threshold.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7ea2b4eba003440e82626f025f783c8f250bd30
Author: Rob Clark <robdclark at gmail.com>
Date:   Thu Jan 18 08:32:22 2018 -0500

    freedreno/ir3: lower phi webs to regs
    
    nir's from_ssa pass is much better at avoiding inserting extra moves
    than our logic is.  And lowering phi webs to regs just treats anything
    involved in a phi web as an array of length=1.  Which with previous
    array related fixes in RA/etc ends up working out quite well.  This cuts
    down on extra instructions and also helps with register pressure.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a6ddf964fb90e4520501868ff00fed66e7814f3
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 12:32:24 2018 -0500

    freedreno/ir3: separate arrays from groups
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=55f14a1ac4553eb14656540404cf9a6a9abc34fc
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 09:54:07 2018 -0500

    freedreno/ir3: make block/instruction serialno per-shader
    
    Makes it easier to compare values seen in-game (where there are many
    shaders) to cmdline standalone compiler.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a7de943927b16fc9142d31f22b815c3e19e96ea
Author: Rob Clark <robdclark at gmail.com>
Date:   Tue Jan 23 09:28:44 2018 -0500

    freedreno/ir3: add spirv support to cmdline compiler
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=942341bcd0128fb9d9caf68b33f603855e2f6d69
Author: Rob Clark <robdclark at gmail.com>
Date:   Sun Jan 21 12:31:51 2018 -0500

    freedreno/ir3: don't lower fsat
    
    Instead, if possible fold (sat) flag into src, otherwise use:
    
      (sat)max.f rD, rS, rS
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2fc94f0745b375b586dbd2685b1c268f4267747
Author: Rob Clark <robdclark at gmail.com>
Date:   Sun Jan 21 12:20:01 2018 -0500

    freedreno/ir3: add encoding/decoding for (sat) bit
    
    Seems to be there since a3xx, but we always lowered fsat.  But we can
    shave some instructions, especially in shaders that use lots of
    clamp(foo, 0.0, 1.0) by not lowering fsat.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b658533e1109b8ff9a6578a7eb4b390454e7876
Author: Rob Clark <robdclark at gmail.com>
Date:   Sun Jan 21 11:13:44 2018 -0500

    freedreno/ir3: extend liverange of arrays
    
    Use livein state of other blocks to extend liverange of arrays when they
    are still needed by successor blocks.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac459a6f7f16dc8a999619fcf12f385ffdbbeda0
Author: Rob Clark <robdclark at gmail.com>
Date:   Fri Jan 19 15:45:37 2018 -0500

    freedreno/ir3: avoid extra mov's for "arrays"
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bc3fb6992b19d55015bd9a9e96f6f0c19af1940
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 16:01:42 2018 -0500

    freedreno/ir3: a couple more array fixes
    
    (Plus a couple TODOs)
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ea1ef41911490c696a7e230511c99f0c9fac060
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:58:49 2018 -0500

    freedreno/ir3: keep array stores
    
    Since these are not in SSA form, add to block's keeps so it doesn't
    appear unused.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c60f150d5613ccfb8146021455500a9ac9c17b89
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:38:06 2018 -0500

    freedreno/ir3: propagate barrier information
    
    When eliminating movs, the instruction that is now directly using the
    src of the mov has the same scheduling order constraints as the original
    mov instruction.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=98702c1010a16fe78e2c4e39e005309cc2b12157
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:35:12 2018 -0500

    freedreno/ir3: remove pointless statement
    
    Function ends after this if/else ladder, so it was pointless.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=930ca0e03862a86b4fe0933661e4220cf114bfb0
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:33:55 2018 -0500

    freedreno/ir3: some more debug prints
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a84e32484778fb535d3ad8a266b884e14ad194da
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:24:17 2018 -0500

    freedreno/ir3: fix printing of relative branch offsets
    
    The number of bits depends on generation.  But printing negative values
    with a5xx encoding (largest size) but compiling for a3xx or a4xx, would
    result in negative values printed as large positive values.
    
    I guess in practice huge negative branch offsets aren't likely (and if
    that is the case, the shader is probably too big to grok by reading the
    assembly).  So just print using smallest bitfield size.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5c28fe07b2822866aaedfe94362918904bd8869
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 15 15:57:52 2018 -0500

    freedreno/ir3: be more clever with if/else jumps
    
    Try to clean up things like:
    
      br !p0.x #2
      br p0.x #something
    
    to eliminate the first branch.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=44dd7dcd2fb0d59cf33bad5313bd45b583002ae4
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 15 14:58:41 2018 -0500

    freedreno/ir3: avoid some spurious sync bits
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=069c0ac62520ef06ec6b8c8f67f364d5be9cbc9a
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 15:28:10 2018 -0500

    freedreno/ir3: print # of sync bits for shaderdb
    
    When trying to optimize to reduce stalls, it is nice to see this info.
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d45e2e39f3a6fd9afa7bd7c25be58c80b2f44ab
Author: Rob Clark <robdclark at gmail.com>
Date:   Mon Jan 29 09:53:30 2018 -0500

    freedreno: add debug trace for flush
    
    Signed-off-by: Rob Clark <robdclark at gmail.com>

More information about the mesa-commit mailing list