Mesa (master): radeonsi: put both tessellation rings into 1 buffer

[Marek Olšák]

Module: Mesa
Branch: master
Commit: fca7dee9c6aa669764d8179e3064ea28b17d2835
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fca7dee9c6aa669764d8179e3064ea28b17d2835

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Feb  3 02:03:08 2018 +0100

radeonsi: put both tessellation rings into 1 buffer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_pipe.c          |  3 +-
 src/gallium/drivers/radeonsi/si_pipe.h          |  3 +-
 src/gallium/drivers/radeonsi/si_state_draw.c    |  2 +-
 src/gallium/drivers/radeonsi/si_state_shaders.c | 39 ++++++++++---------------
 4 files changed, 18 insertions(+), 29 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index b3cfc83ac5..3d787d58cd 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -117,8 +117,7 @@ static void si_destroy_context(struct pipe_context *context)
 
 	pipe_resource_reference(&sctx->esgs_ring, NULL);
 	pipe_resource_reference(&sctx->gsvs_ring, NULL);
-	pipe_resource_reference(&sctx->tf_ring, NULL);
-	pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
+	pipe_resource_reference(&sctx->tess_rings, NULL);
 	pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
 	r600_resource_reference(&sctx->border_color_buffer, NULL);
 	free(sctx->border_color_table);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 7b23e8c9d7..896b640c17 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -512,8 +512,7 @@ struct si_context {
 	struct pipe_constant_buffer	null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 	struct pipe_resource		*esgs_ring;
 	struct pipe_resource		*gsvs_ring;
-	struct pipe_resource		*tf_ring;
-	struct pipe_resource		*tess_offchip_ring;
+	struct pipe_resource		*tess_rings;
 	union pipe_color_union		*border_color_table; /* in CPU memory, any endian */
 	struct r600_resource		*border_color_buffer;
 	union pipe_color_union		*border_color_map; /* in VRAM (slow access), little endian */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index b245a38398..3881e3f2a6 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -296,7 +296,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	/* Set userdata SGPRs for TES. */
 	radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
 	radeon_emit(cs, offchip_layout);
-	radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16);
+	radeon_emit(cs, r600_resource(sctx->tess_rings)->gpu_address >> 16);
 
 	ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
 		       S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 0d1dba15b8..701f7aa575 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2970,38 +2970,29 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
-	assert(!sctx->tf_ring);
+	assert(!sctx->tess_rings);
 
 	/* Use 64K alignment for both rings, so that we can pass the address
 	 * to shaders as one SGPR containing bits [16:47].
 	 */
-	sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
-						 R600_RESOURCE_FLAG_UNMAPPABLE,
-						 PIPE_USAGE_DEFAULT,
-						 sctx->screen->tess_factor_ring_size,
-						 64 * 1024);
-	if (!sctx->tf_ring)
-		return;
-
-	sctx->tess_offchip_ring =
-		si_aligned_buffer_create(sctx->b.b.screen,
-					 R600_RESOURCE_FLAG_UNMAPPABLE,
-					 PIPE_USAGE_DEFAULT,
-					 sctx->screen->tess_offchip_ring_size,
-					 64 * 1024);
-	if (!sctx->tess_offchip_ring)
+	sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
+						    R600_RESOURCE_FLAG_UNMAPPABLE,
+						    PIPE_USAGE_DEFAULT,
+						    align(sctx->screen->tess_offchip_ring_size,
+							  64 * 1024) +
+						    sctx->screen->tess_factor_ring_size,
+						    64 * 1024);
+	if (!sctx->tess_rings)
 		return;
 
 	si_init_config_add_vgt_flush(sctx);
 
-	uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
-	uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
+	uint64_t offchip_va = r600_resource(sctx->tess_rings)->gpu_address;
 	assert((offchip_va & 0xffff) == 0);
-	assert((factor_va & 0xffff) == 0);
+	uint64_t factor_va = offchip_va +
+			     align(sctx->screen->tess_offchip_ring_size, 64 * 1024);
 
-	si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
-		      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
-	si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
+	si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
 		      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
 
 	/* Append these registers to the init config state. */
@@ -3138,9 +3129,9 @@ bool si_update_shaders(struct si_context *sctx)
 
 	/* Update stages before GS. */
 	if (sctx->tes_shader.cso) {
-		if (!sctx->tf_ring) {
+		if (!sctx->tess_rings) {
 			si_init_tess_factor_ring(sctx);
-			if (!sctx->tf_ring)
+			if (!sctx->tess_rings)
 				return false;
 		}