Mesa (master): intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

[Matt Turner]

Module: Mesa
Branch: master
Commit: b5d8781e19559a8f9850f1a900ef93ffa3617faa
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5d8781e19559a8f9850f1a900ef93ffa3617faa

Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jun 14 11:06:45 2017 -0700

intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

If multiple instructions are emitted, special handling of things like
conditional mod and NoDDClr/NoDDChk need to be performed.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/intel/compiler/brw_fs.h             |  2 +-
 src/intel/compiler/brw_fs_generator.cpp | 10 +++++++---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 63373580ee..37106ccb28 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -409,7 +409,7 @@ private:
    void generate_urb_write(fs_inst *inst, struct brw_reg payload);
    void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
    void generate_barrier(fs_inst *inst, struct brw_reg src);
-   void generate_linterp(fs_inst *inst, struct brw_reg dst,
+   bool generate_linterp(fs_inst *inst, struct brw_reg dst,
 			 struct brw_reg *src);
    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
                      struct brw_reg surface_index,
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index bba917d755..3abd7cf538 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -646,9 +646,9 @@ fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
    brw_WAIT(p);
 }
 
-void
+bool
 fs_generator::generate_linterp(fs_inst *inst,
-			     struct brw_reg dst, struct brw_reg *src)
+                               struct brw_reg dst, struct brw_reg *src)
 {
    /* PLN reads:
     *                      /   in SIMD16   \
@@ -678,6 +678,8 @@ fs_generator::generate_linterp(fs_inst *inst,
    if (devinfo->has_pln &&
        (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
       brw_PLN(p, dst, interp, delta_x);
+
+      return false;
    } else {
       i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
       i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
@@ -689,6 +691,8 @@ fs_generator::generate_linterp(fs_inst *inst,
        * the first instruction.
        */
       brw_inst_set_saturate(p->devinfo, i[0], false);
+
+      return true;
    }
 }
 
@@ -1963,7 +1967,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
 	 brw_MOV(p, dst, src[0]);
 	 break;
       case FS_OPCODE_LINTERP:
-	 generate_linterp(inst, dst, src);
+	 multiple_instructions_emitted = generate_linterp(inst, dst, src);
 	 break;
       case FS_OPCODE_PIXEL_X:
          assert(src[0].type == BRW_REGISTER_TYPE_UW);