Mesa (master): broadcom/vc5: Disable early Z when the stencil func isn' t ALWAYS.
Eric Anholt
anholt at kemper.freedesktop.org
Wed Jan 3 22:36:11 UTC 2018
Module: Mesa
Branch: master
Commit: 7836c85919a289e806c4dbd3e7d080914049b130
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7836c85919a289e806c4dbd3e7d080914049b130
Author: Eric Anholt <eric at anholt.net>
Date: Thu Dec 28 15:42:14 2017 -0800
broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.
Apparently the other funcs will have observable differences when early Z
is enabled.
Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
---
src/gallium/drivers/vc5/vc5_state.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc5/vc5_state.c b/src/gallium/drivers/vc5/vc5_state.c
index 35d5e1df50..0d6699ae57 100644
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -165,8 +165,10 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
cso->depth.func == PIPE_FUNC_LEQUAL) &&
(!cso->stencil[0].enabled ||
(cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
+ cso->stencil[0].func == PIPE_FUNC_ALWAYS &&
(!cso->stencil[1].enabled ||
- cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
+ (cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP &&
+ cso->stencil[1].func == PIPE_FUNC_ALWAYS)))));
}
const struct pipe_stencil_state *front = &cso->stencil[0];
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