Mesa (master): nvc0: update tic in-place when buffer address changes

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: bdf300e09d8ddbcacac5d7c8d727e5c2f5635f50
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdf300e09d8ddbcacac5d7c8d727e5c2f5635f50

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Dec 30 01:07:30 2017 -0500

nvc0: update tic in-place when buffer address changes

This is helpful for bindless, where changing TIC id's is undesirable.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/nvc0/nvc0_context.h |  2 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_tex.c     | 33 +++++++++++++++----------
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 6f631b993c..f0eabb02fe 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -345,7 +345,7 @@ void nvc0_validate_surfaces(struct nvc0_context *);
 void nve4_set_surface_info(struct nouveau_pushbuf *, struct pipe_image_view *,
                            struct nvc0_context *);
 void nvc0_mark_image_range_valid(const struct pipe_image_view *);
-void nvc0_update_tic(struct nvc0_context *, struct nv50_tic_entry *,
+bool nvc0_update_tic(struct nvc0_context *, struct nv50_tic_entry *,
                      struct nv04_resource *);
 
 struct pipe_sampler_view *
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index e57391e9a3..5ed1d06ce2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -449,23 +449,30 @@ nvc0_create_texture_view(struct pipe_context *pipe,
    return gf100_create_texture_view(pipe, texture, templ, flags, target);
 }
 
-void
+bool
 nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
                 struct nv04_resource *res)
 {
    uint64_t address = res->address;
    if (res->base.target != PIPE_BUFFER)
-      return;
+      return false;
    address += tic->pipe.u.buf.offset;
    if (tic->tic[1] == (uint32_t)address &&
        (tic->tic[2] & 0xff) == address >> 32)
-      return;
+      return false;
 
-   nvc0_screen_tic_unlock(nvc0->screen, tic);
-   tic->id = -1;
    tic->tic[1] = address;
    tic->tic[2] &= 0xffffff00;
    tic->tic[2] |= address >> 32;
+
+   if (tic->id >= 0) {
+      nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32,
+                           NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
+                           tic->tic);
+      return true;
+   }
+
+   return false;
 }
 
 bool
@@ -488,14 +495,14 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
          continue;
       }
       res = nv04_resource(tic->pipe.texture);
-      nvc0_update_tic(nvc0, tic, res);
+      need_flush |= nvc0_update_tic(nvc0, tic, res);
 
       if (tic->id < 0) {
          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 
-         nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
-                               NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
-                               tic->tic);
+         nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32,
+                              NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
+                              tic->tic);
          need_flush = true;
       } else
       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
@@ -554,14 +561,14 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
          continue;
       }
       res = nv04_resource(tic->pipe.texture);
-      nvc0_update_tic(nvc0, tic, res);
+      need_flush |= nvc0_update_tic(nvc0, tic, res);
 
       if (tic->id < 0) {
          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 
-         nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
-                               NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
-                               tic->tic);
+         nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32,
+                              NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
+                              tic->tic);
          need_flush = true;
       } else
       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {