Mesa (master): Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 8045f01e2a1879b1266281e64fe292b038766168
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8045f01e2a1879b1266281e64fe292b038766168

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Jan 15 13:47:18 2018 +0100

Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"

This can't work for two reasons:
- TESSINNER/TESSOUTER are shader input values, so never translated
to the intrinsic ops
- the shader info pass scans the current stage but we want to know
in TCS, if TES reads the tess factors.

This fixes 6 regressions related to
deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes

This reverts commit 5ba1a61648e2dea96f621a5886ad8b937a471ab4.

---

 src/amd/common/ac_nir_to_llvm.c | 2 +-
 src/amd/common/ac_nir_to_llvm.h | 1 +
 src/amd/common/ac_shader_info.c | 4 ----
 src/amd/common/ac_shader_info.h | 3 ---
 src/amd/vulkan/radv_pipeline.c  | 2 ++
 5 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index d4c24342d7..2034039543 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6310,7 +6310,7 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
 					    16 + tf_offset, 1, 0, true, false);
 
 	//store to offchip for TES to read - only if TES reads them
-	if (ctx->shader_info->info.tes.reads_tess_factors) {
+	if (ctx->options->key.tcs.tes_reads_tess_factors) {
 		LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
 		LLVMValueRef tf_inner_offset;
 		unsigned param_outer, param_inner;
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 70cecd6a62..1737866166 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -55,6 +55,7 @@ struct ac_tcs_variant_key {
 	struct ac_vs_variant_key vs_key;
 	unsigned primitive_mode;
 	unsigned input_vertices;
+	uint32_t tes_reads_tess_factors:1;
 };
 
 struct ac_fs_variant_key {
diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index 7261261850..5716ec043d 100644
--- a/src/amd/common/ac_shader_info.c
+++ b/src/amd/common/ac_shader_info.c
@@ -106,10 +106,6 @@ gather_intrinsic_info(const nir_intrinsic_instr *instr,
 		mark_sampler_desc(instr->variables[0]->var, info);
 		break;
 	}
-	case nir_intrinsic_load_tess_level_inner:
-	case nir_intrinsic_load_tess_level_outer:
-		info->tes.reads_tess_factors = true;
-		break;
 	default:
 		break;
 	}
diff --git a/src/amd/common/ac_shader_info.h b/src/amd/common/ac_shader_info.h
index fbafeb9f0e..2be61679fc 100644
--- a/src/amd/common/ac_shader_info.h
+++ b/src/amd/common/ac_shader_info.h
@@ -49,9 +49,6 @@ struct ac_shader_info {
 		bool uses_thread_id[3];
 		bool uses_local_invocation_idx;
 	} cs;
-	struct {
-		bool reads_tess_factors;
-	} tes;
 };
 
 /* A NIR pass to gather all the info needed to optimise the allocation patterns
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 0bb1cd9dff..c3c17af850 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1759,6 +1759,8 @@ radv_fill_shader_keys(struct ac_shader_variant_key *keys,
 		keys[MESA_SHADER_VERTEX].vs.as_ls = true;
 		keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
 		keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
+
+		keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
 	}
 
 	if (nir[MESA_SHADER_GEOMETRY]) {