Mesa (master): intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_CHANNEL.
Francisco Jerez
currojerez at kemper.freedesktop.org
Fri Mar 2 19:37:29 UTC 2018
Module: Mesa
Branch: master
Commit: 6edb332b44b2570abac8fea2123050ea0f84e1e6
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6edb332b44b2570abac8fea2123050ea0f84e1e6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 22 12:49:01 2018 -0800
intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_CHANNEL.
This shouldn't cause any functional change at this point, it changes
SHADER_OPCODE_FIND_LIVE_CHANNEL to use the flag register specified at
the IR level instead of the hard-coded f1.0, now that it can be
represented in backend_instruction::flag_subreg. This will be
necessary for scheduling to behave correctly once more things start
making use of f1.0.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/intel/compiler/brw_eu_emit.c | 5 +++--
src/intel/compiler/brw_fs.cpp | 3 ++-
src/intel/compiler/brw_fs_builder.h | 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index a96fe43556..14b1c592b6 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3399,7 +3399,9 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
*/
inst = brw_FBL(p, vec1(dst), exec_mask);
} else {
- const struct brw_reg flag = brw_flag_reg(1, 0);
+ const struct brw_reg flag = brw_flag_reg(
+ brw_inst_flag_reg_nr(devinfo, p->current),
+ brw_inst_flag_subreg_nr(devinfo, p->current));
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_MOV(p, retype(flag, BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
@@ -3418,7 +3420,6 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
brw_inst_set_group(devinfo, inst, lower_size * i + 8 * qtr_control);
brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
- brw_inst_set_flag_reg_nr(devinfo, inst, 1);
brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1);
}
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 16b6a06c69..c255a3b23b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -931,7 +931,8 @@ fs_inst::flags_written() const
if ((conditional_mod && (opcode != BRW_OPCODE_SEL &&
opcode != BRW_OPCODE_IF &&
opcode != BRW_OPCODE_WHILE)) ||
- opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS) {
+ opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS ||
+ opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL) {
return flag_mask(this);
} else {
return flag_mask(dst, size_written);
diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index 874272b7af..b157e33c39 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -406,7 +406,7 @@ namespace brw {
const dst_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD);
const dst_reg dst = vgrf(src.type);
- ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
+ ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index)->flag_subreg = 2;
ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
return src_reg(component(dst, 0));
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