Mesa (master): ac/nir: rename radeon_llvm_reg_index_soa() to ac_llvm_reg_index_soa()

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 7c834306724881a859f7ac2a48ad71fd8b882765
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c834306724881a859f7ac2a48ad71fd8b882765

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Mar 13 14:59:11 2018 +0100

ac/nir: rename radeon_llvm_reg_index_soa() to ac_llvm_reg_index_soa()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c   |  6 +++---
 src/amd/common/ac_nir_to_llvm.h   |  2 +-
 src/amd/vulkan/radv_nir_to_llvm.c | 16 ++++++++--------
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bdb2da6bea..5d701cb011 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2066,7 +2066,7 @@ static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
 					LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
 						LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
 								ctx->ac.i32, ""), "");
-			fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
+			fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
 		}
 		sample_index = adjust_sample_index_using_fmask(&ctx->ac,
 							       fmask_load_address[0],
@@ -2091,7 +2091,7 @@ static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
 			for (chan = 0; chan < 2; ++chan)
 				coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
 						ctx->ac.i32, ""), "");
-			coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
+			coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
 			count++;
 		}
 
@@ -3700,7 +3700,7 @@ ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
 
 	for (unsigned i = 0; i < attrib_count; ++i) {
 		for (unsigned chan = 0; chan < 4; chan++) {
-			abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
+			abi->outputs[ac_llvm_reg_index_soa(output_loc + i, chan)] =
 		                       ac_build_alloca_undef(ctx, ctx->f32, "");
 		}
 	}
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index c5cc98d6eb..ca1da33ca5 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -40,7 +40,7 @@ struct ac_shader_abi;
 #define INTERP_CENTROID 1
 #define INTERP_SAMPLE 2
 
-static inline unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
+static inline unsigned ac_llvm_reg_index_soa(unsigned index, unsigned chan)
 {
 	return (index * 4) + chan;
 }
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index bac71c53c7..056eb23ab6 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1795,7 +1795,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
 
 		for (unsigned chan = 0; chan < 4; chan++) {
 			LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
-			ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
+			ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
 				ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
 							input, llvm_chan, ""));
 		}
@@ -1878,7 +1878,7 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
 		interp = NULL;
 
 	for (unsigned i = 0; i < attrib_count; ++i)
-		ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
+		ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
 
 }
 
@@ -1933,7 +1933,7 @@ handle_fs_inputs(struct radv_shader_context *ctx,
 
 	for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
 		LLVMValueRef interp_param;
-		LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
+		LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
 
 		if (!(ctx->input_mask & (1ull << i)))
 			continue;
@@ -1959,7 +1959,7 @@ handle_fs_inputs(struct radv_shader_context *ctx,
 	ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
 
 	if (ctx->shader_info->info.needs_multiview_view_index)
-		ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
+		ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
 }
 
 static void
@@ -2156,7 +2156,7 @@ static LLVMValueRef
 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
 {
 	LLVMValueRef output =
-		ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
+		ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
 
 	return LLVMBuildLoad(ctx->ac.builder, output, "");
 }
@@ -2174,10 +2174,10 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
 	int i;
 
 	if (ctx->options->key.has_multiview_view_index) {
-		LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
+		LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
 		if(!*tmp_out) {
 			for(unsigned i = 0; i < 4; ++i)
-				ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
+				ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
 				            ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
 		}
 
@@ -3396,7 +3396,7 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
 						     0, 1, 1, true, false);
 
 			LLVMBuildStore(ctx->ac.builder,
-				       ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
+				       ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
 		}
 		idx += slot_inc;
 	}