Mesa (master): i965: pipecontrol: add LRI write immediate flag
Lionel Landwerlin
llandwerlin at kemper.freedesktop.org
Tue Mar 20 16:59:16 UTC 2018
Module: Mesa
Branch: master
Commit: d3e5d3955c1232aa405cf9ac3af65d4d377fd81a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3e5d3955c1232aa405cf9ac3af65d4d377fd81a
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Mar 15 12:11:15 2018 +0000
i965: pipecontrol: add LRI write immediate flag
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_pipe_control.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.h b/src/mesa/drivers/dri/i965/brw_pipe_control.h
index 651cd4d3e7..4c58e16660 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.h
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.h
@@ -34,6 +34,7 @@ struct brw_bo;
* additional flushing control.
*/
#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_LRI_WRITE_IMMEDIATE (1 << 23) /* Gen7+ */
#define PIPE_CONTROL_CS_STALL (1 << 20)
#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19)
#define PIPE_CONTROL_TLB_INVALIDATE (1 << 18)
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