Mesa (master): intel/genxml: Add SAMPLER_INSTDONE register.
Rafael Antognolli
rantogno at kemper.freedesktop.org
Mon Mar 26 16:26:13 UTC 2018
Module: Mesa
Branch: master
Commit: 70d7c70e8dcc74674cebcb9877cf71f44db6c924
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70d7c70e8dcc74674cebcb9877cf71f44db6c924
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Wed Mar 21 11:42:22 2018 -0700
intel/genxml: Add SAMPLER_INSTDONE register.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
src/intel/genxml/gen10.xml | 23 +++++++++++++++++++++++
src/intel/genxml/gen11.xml | 23 +++++++++++++++++++++++
src/intel/genxml/gen7.xml | 22 ++++++++++++++++++++++
src/intel/genxml/gen75.xml | 25 +++++++++++++++++++++++++
src/intel/genxml/gen8.xml | 23 +++++++++++++++++++++++
src/intel/genxml/gen9.xml | 23 +++++++++++++++++++++++
6 files changed, 139 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index afdb580b62..aeb9966759 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3504,6 +3504,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
+ <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
+ <field name="IME Done" start="0" end="0" type="bool"/>
+ <field name="PL0 Done" start="1" end="1" type="bool"/>
+ <field name="SO0 Done" start="2" end="2" type="bool"/>
+ <field name="DG0 Done" start="3" end="3" type="bool"/>
+ <field name="FT0 Done" start="4" end="4" type="bool"/>
+ <field name="DM0 Done" start="5" end="5" type="bool"/>
+ <field name="SC Done" start="6" end="6" type="bool"/>
+ <field name="FL0 Done" start="7" end="7" type="bool"/>
+ <field name="QC Done" start="8" end="8" type="bool"/>
+ <field name="SVSM Done" start="9" end="9" type="bool"/>
+ <field name="SI0 Done" start="10" end="10" type="bool"/>
+ <field name="MT0 Done" start="11" end="11" type="bool"/>
+ <field name="AVS Done" start="12" end="12" type="bool"/>
+ <field name="IEF Done" start="13" end="13" type="bool"/>
+ <field name="CRE Done" start="14" end="14" type="bool"/>
+ <field name="SVSM_ARB_SIFM" start="15" end="15" type="bool"/>
+ <field name="SVSM ARB2" start="16" end="16" type="bool"/>
+ <field name="SVSM ARB1" start="17" end="17" type="bool"/>
+ <field name="SVSM Adapter" start="18" end="18" type="bool"/>
+ <field name="BDM Done" start="19" end="19" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index a5e67c30bf..6ca0e785ba 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3500,6 +3500,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
+ <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
+ <field name="IME Done" start="0" end="0" type="bool"/>
+ <field name="PL0 Done" start="1" end="1" type="bool"/>
+ <field name="SO0 Done" start="2" end="2" type="bool"/>
+ <field name="DG0 Done" start="3" end="3" type="bool"/>
+ <field name="FT0 Done" start="4" end="4" type="bool"/>
+ <field name="DM0 Done" start="5" end="5" type="bool"/>
+ <field name="SC Done" start="6" end="6" type="bool"/>
+ <field name="FL0 Done" start="7" end="7" type="bool"/>
+ <field name="QC Done" start="8" end="8" type="bool"/>
+ <field name="SVSM Done" start="9" end="9" type="bool"/>
+ <field name="SI0 Done" start="10" end="10" type="bool"/>
+ <field name="MT0 Done" start="11" end="11" type="bool"/>
+ <field name="AVS Done" start="12" end="12" type="bool"/>
+ <field name="IEF Done" start="13" end="13" type="bool"/>
+ <field name="CRE Done" start="14" end="14" type="bool"/>
+ <field name="SVSM_ARB_SIFM" start="15" end="15" type="bool"/>
+ <field name="SVSM ARB2" start="16" end="16" type="bool"/>
+ <field name="SVSM ARB1" start="17" end="17" type="bool"/>
+ <field name="SVSM Adapter" start="18" end="18" type="bool"/>
+ <field name="BDM Done" start="19" end="19" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 52ca043b51..4865843fcb 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2436,6 +2436,28 @@
<field name="MA1 Done" start="25" end="25" type="bool"/>
</register>
+ <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
+ <field name="VME Done" start="0" end="0" type="bool"/>
+ <field name="PL0 Done" start="1" end="1" type="bool"/>
+ <field name="SO0 Done" start="2" end="2" type="bool"/>
+ <field name="DG0 Done" start="3" end="3" type="bool"/>
+ <field name="FT0 Done" start="4" end="4" type="bool"/>
+ <field name="DM0 Done" start="5" end="5" type="bool"/>
+ <field name="SC Done" start="6" end="6" type="bool"/>
+ <field name="FL0 Done" start="7" end="7" type="bool"/>
+ <field name="QC Done" start="8" end="8" type="bool"/>
+ <field name="SVSM Done" start="9" end="9" type="bool"/>
+ <field name="SI0 Done" start="10" end="10" type="bool"/>
+ <field name="MT0 Done" start="11" end="11" type="bool"/>
+ <field name="AVS Done" start="12" end="12" type="bool"/>
+ <field name="IEF Done" start="13" end="13" type="bool"/>
+ <field name="VDI Done" start="14" end="14" type="bool"/>
+ <field name="SVSM ARB3" start="15" end="15" type="bool"/>
+ <field name="SVSM ARB2" start="16" end="16" type="bool"/>
+ <field name="SVSM ARB1" start="17" end="17" type="bool"/>
+ <field name="SVSM Adapter" start="18" end="18" type="bool"/>
+ </register>
+
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9501ec53f8..da06e84ee9 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2908,6 +2908,31 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
+ <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
+ <field name="IME Done" start="0" end="0" type="bool"/>
+ <field name="PL0 Done" start="1" end="1" type="bool"/>
+ <field name="SO0 Done" start="2" end="2" type="bool"/>
+ <field name="DG0 Done" start="3" end="3" type="bool"/>
+ <field name="FT0 Done" start="4" end="4" type="bool"/>
+ <field name="DM0 Done" start="5" end="5" type="bool"/>
+ <field name="SC Done" start="6" end="6" type="bool"/>
+ <field name="FL0 Done" start="7" end="7" type="bool"/>
+ <field name="QC Done" start="8" end="8" type="bool"/>
+ <field name="SVSM Done" start="9" end="9" type="bool"/>
+ <field name="SI0 Done" start="10" end="10" type="bool"/>
+ <field name="MT0 Done" start="11" end="11" type="bool"/>
+ <field name="AVS Done" start="12" end="12" type="bool"/>
+ <field name="IEF Done" start="13" end="13" type="bool"/>
+ <field name="CRE Done" start="14" end="14" type="bool"/>
+ <field name="SVSM ARB3" start="15" end="15" type="bool"/>
+ <field name="SVSM ARB2" start="16" end="16" type="bool"/>
+ <field name="SVSM ARB1" start="17" end="17" type="bool"/>
+ <field name="SVSM Adapter" start="18" end="18" type="bool"/>
+ <field name="FT1 Done" start="19" end="19" type="bool"/>
+ <field name="DM1 Done" start="20" end="20" type="bool"/>
+ <field name="MT1 Done" start="21" end="21" type="bool"/>
+ </register>
+
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 10dc787f48..71626c15cd 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3165,6 +3165,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
+ <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
+ <field name="IME Done" start="0" end="0" type="bool"/>
+ <field name="PL0 Done" start="1" end="1" type="bool"/>
+ <field name="SO0 Done" start="2" end="2" type="bool"/>
+ <field name="DG0 Done" start="3" end="3" type="bool"/>
+ <field name="FT0 Done" start="4" end="4" type="bool"/>
+ <field name="DM0 Done" start="5" end="5" type="bool"/>
+ <field name="SC Done" start="6" end="6" type="bool"/>
+ <field name="FL0 Done" start="7" end="7" type="bool"/>
+ <field name="QC Done" start="8" end="8" type="bool"/>
+ <field name="SVSM Done" start="9" end="9" type="bool"/>
+ <field name="SI0 Done" start="10" end="10" type="bool"/>
+ <field name="MT0 Done" start="11" end="11" type="bool"/>
+ <field name="AVS Done" start="12" end="12" type="bool"/>
+ <field name="IEF Done" start="13" end="13" type="bool"/>
+ <field name="CRE Done" start="14" end="14" type="bool"/>
+ <field name="SVSM ARB3" start="15" end="15" type="bool"/>
+ <field name="SVSM ARB2" start="16" end="16" type="bool"/>
+ <field name="SVSM ARB1" start="17" end="17" type="bool"/>
+ <field name="SVSM Adapter" start="18" end="18" type="bool"/>
+ <field name="BDM Done" start="19" end="19" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 90d3a15eb2..c32f2c3162 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3450,6 +3450,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
+ <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
+ <field name="IME Done" start="0" end="0" type="bool"/>
+ <field name="PL0 Done" start="1" end="1" type="bool"/>
+ <field name="SO0 Done" start="2" end="2" type="bool"/>
+ <field name="DG0 Done" start="3" end="3" type="bool"/>
+ <field name="FT0 Done" start="4" end="4" type="bool"/>
+ <field name="DM0 Done" start="5" end="5" type="bool"/>
+ <field name="SC Done" start="6" end="6" type="bool"/>
+ <field name="FL0 Done" start="7" end="7" type="bool"/>
+ <field name="QC Done" start="8" end="8" type="bool"/>
+ <field name="SVSM Done" start="9" end="9" type="bool"/>
+ <field name="SI0 Done" start="10" end="10" type="bool"/>
+ <field name="MT0 Done" start="11" end="11" type="bool"/>
+ <field name="AVS Done" start="12" end="12" type="bool"/>
+ <field name="IEF Done" start="13" end="13" type="bool"/>
+ <field name="CRE Done" start="14" end="14" type="bool"/>
+ <field name="SVSM ARB3" start="15" end="15" type="bool"/>
+ <field name="SVSM ARB2" start="16" end="16" type="bool"/>
+ <field name="SVSM ARB1" start="17" end="17" type="bool"/>
+ <field name="SVSM Adapter" start="18" end="18" type="bool"/>
+ <field name="BDM Done" start="19" end="19" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
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