Mesa (master): intel/genxml: Add SC_INSTDONE register.
Rafael Antognolli
rantogno at kemper.freedesktop.org
Mon Mar 26 16:26:12 UTC 2018
Module: Mesa
Branch: master
Commit: 4c0ae36143d292745e44103a3394ff0fadfdcbe6
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c0ae36143d292745e44103a3394ff0fadfdcbe6
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Wed Mar 21 11:42:20 2018 -0700
intel/genxml: Add SC_INSTDONE register.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
src/intel/genxml/gen10.xml | 27 +++++++++++++++++++++++++++
src/intel/genxml/gen11.xml | 27 +++++++++++++++++++++++++++
src/intel/genxml/gen7.xml | 19 +++++++++++++++++++
src/intel/genxml/gen75.xml | 17 +++++++++++++++++
src/intel/genxml/gen8.xml | 24 ++++++++++++++++++++++++
src/intel/genxml/gen9.xml | 26 ++++++++++++++++++++++++++
6 files changed, 140 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index cc696e800d..e0bf0e9159 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3459,6 +3459,33 @@
<field name="GAM Done" start="31" end="31" type="bool"/>
</register>
+ <register name="SC_INSTDONE" length="1" num="0x7100">
+ <field name="SVL Done" start="0" end="0" type="bool"/>
+ <field name="WMFE Done" start="1" end="1" type="bool"/>
+ <field name="WMBE Done" start="2" end="2" type="bool"/>
+ <field name="HIZ Done" start="3" end="3" type="bool"/>
+ <field name="STC Done" start="4" end="4" type="bool"/>
+ <field name="IZ Done" start="5" end="5" type="bool"/>
+ <field name="SBE Done" start="6" end="6" type="bool"/>
+ <field name="RCZ Done" start="8" end="8" type="bool"/>
+ <field name="RCC Done" start="9" end="9" type="bool"/>
+ <field name="RCPBE Done" start="10" end="10" type="bool"/>
+ <field name="RCPFE Done" start="11" end="11" type="bool"/>
+ <field name="DAPB Done" start="12" end="12" type="bool"/>
+ <field name="DAPRBE Done" start="13" end="13" type="bool"/>
+ <field name="SARB Done" start="15" end="15" type="bool"/>
+ <field name="DC0 Done" start="16" end="16" type="bool"/>
+ <field name="DC1 Done" start="17" end="17" type="bool"/>
+ <field name="DC2 Done" start="18" end="18" type="bool"/>
+ <field name="DC3 Done" start="19" end="19" type="bool"/>
+ <field name="GW0 Done" start="20" end="20" type="bool"/>
+ <field name="GW1 Done" start="21" end="21" type="bool"/>
+ <field name="GW2 Done" start="22" end="22" type="bool"/>
+ <field name="GW3 Done" start="23" end="23" type="bool"/>
+ <field name="TDC Done" start="24" end="24" type="bool"/>
+ <field name="SFBE Done" start="25" end="25" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 417fac1365..3278f35b82 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3455,6 +3455,33 @@
<field name="GAC Done" start="31" end="31" type="bool"/>
</register>
+ <register name="SC_INSTDONE" length="1" num="0x7100">
+ <field name="SVL Done" start="0" end="0" type="bool"/>
+ <field name="WMFE Done" start="1" end="1" type="bool"/>
+ <field name="WMBE Done" start="2" end="2" type="bool"/>
+ <field name="HIZ Done" start="3" end="3" type="bool"/>
+ <field name="STC Done" start="4" end="4" type="bool"/>
+ <field name="IZ Done" start="5" end="5" type="bool"/>
+ <field name="SBE Done" start="6" end="6" type="bool"/>
+ <field name="RCZ Done" start="8" end="8" type="bool"/>
+ <field name="RCC Done" start="9" end="9" type="bool"/>
+ <field name="RCPBE Done" start="10" end="10" type="bool"/>
+ <field name="RCPFE Done" start="11" end="11" type="bool"/>
+ <field name="DAPB Done" start="12" end="12" type="bool"/>
+ <field name="DAPRBE Done" start="13" end="13" type="bool"/>
+ <field name="SARB Done" start="15" end="15" type="bool"/>
+ <field name="DC0 Done" start="16" end="16" type="bool"/>
+ <field name="DC1 Done" start="17" end="17" type="bool"/>
+ <field name="DC2 Done" start="18" end="18" type="bool"/>
+ <field name="DC3 Done" start="19" end="19" type="bool"/>
+ <field name="GW0 Done" start="20" end="20" type="bool"/>
+ <field name="GW1 Done" start="21" end="21" type="bool"/>
+ <field name="GW2 Done" start="22" end="22" type="bool"/>
+ <field name="GW3 Done" start="23" end="23" type="bool"/>
+ <field name="TDC Done" start="24" end="24" type="bool"/>
+ <field name="SFBE Done" start="25" end="25" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 87e05c94ef..bc9fa5b65d 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2397,6 +2397,25 @@
<field name="GAC Done" start="31" end="31" type="bool"/>
</register>
+ <register name="SC_INSTDONE" length="1" num="0x7100">
+ <field name="SVL Done" start="0" end="0" type="bool"/>
+ <field name="WMFE Done" start="1" end="1" type="bool"/>
+ <field name="WMBE Done" start="2" end="2" type="bool"/>
+ <field name="HIZ Done" start="3" end="3" type="bool"/>
+ <field name="STC Done" start="4" end="4" type="bool"/>
+ <field name="IZ Done" start="5" end="5" type="bool"/>
+ <field name="SBE Done" start="6" end="6" type="bool"/>
+ <field name="RCZ Done" start="8" end="8" type="bool"/>
+ <field name="RCC Done" start="9" end="9" type="bool"/>
+ <field name="RCPBE Done" start="10" end="10" type="bool"/>
+ <field name="RCPFE Done" start="11" end="11" type="bool"/>
+ <field name="DAPB Done" start="12" end="12" type="bool"/>
+ <field name="DAPRBE Done" start="13" end="13" type="bool"/>
+ <field name="IECP Done" start="14" end="14" type="bool"/>
+ <field name="SARB Done" start="15" end="15" type="bool"/>
+ <field name="VSC Done" start="16" end="16" type="bool"/>
+ </register>
+
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 68aff857f3..9e2b789006 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2869,6 +2869,23 @@
<field name="GAM Done" start="31" end="31" type="uint" default="1"/>
</register>
+ <register name="SC_INSTDONE" length="1" num="0x7100">
+ <field name="SVL Done" start="0" end="0" type="bool"/>
+ <field name="WMFE Done" start="1" end="1" type="bool"/>
+ <field name="WMBE Done" start="2" end="2" type="bool"/>
+ <field name="HIZ Done" start="3" end="3" type="bool"/>
+ <field name="STC Done" start="4" end="4" type="bool"/>
+ <field name="IZ Done" start="5" end="5" type="bool"/>
+ <field name="SBE Done" start="6" end="6" type="bool"/>
+ <field name="RCZ Done" start="8" end="8" type="bool"/>
+ <field name="RCC Done" start="9" end="9" type="bool"/>
+ <field name="RCPBE Done" start="10" end="10" type="bool"/>
+ <field name="RCPFE Done" start="11" end="11" type="bool"/>
+ <field name="DAPB Done" start="12" end="12" type="bool"/>
+ <field name="DAPRBE Done" start="13" end="13" type="bool"/>
+ <field name="SARB Done" start="15" end="15" type="bool"/>
+ </register>
+
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 8a4bf34cf7..0a6be59698 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3123,6 +3123,30 @@
<field name="GAM Done" start="31" end="31" type="bool"/>
</register>
+ <register name="SC_INSTDONE" length="1" num="0x7100">
+ <field name="SVL Done" start="0" end="0" type="bool"/>
+ <field name="WMFE Done" start="1" end="1" type="bool"/>
+ <field name="WMBE Done" start="2" end="2" type="bool"/>
+ <field name="HIZ Done" start="3" end="3" type="bool"/>
+ <field name="STC Done" start="4" end="4" type="bool"/>
+ <field name="IZ Done" start="5" end="5" type="bool"/>
+ <field name="SBE Done" start="6" end="6" type="bool"/>
+ <field name="RCZ Done" start="8" end="8" type="bool"/>
+ <field name="RCC Done" start="9" end="9" type="bool"/>
+ <field name="RCPBE Done" start="10" end="10" type="bool"/>
+ <field name="RCPFE Done" start="11" end="11" type="bool"/>
+ <field name="DAPB Done" start="12" end="12" type="bool"/>
+ <field name="DAPRBE Done" start="13" end="13" type="bool"/>
+ <field name="SARB Done" start="15" end="15" type="bool"/>
+ <field name="DC0 Done" start="16" end="16" type="bool"/>
+ <field name="DC1 Done" start="17" end="17" type="bool"/>
+ <field name="DC2 Done" start="18" end="18" type="bool"/>
+ <field name="GW0 Done" start="20" end="20" type="bool"/>
+ <field name="GW1 Done" start="21" end="21" type="bool"/>
+ <field name="GW2 Done" start="22" end="22" type="bool"/>
+ <field name="TDC Done" start="24" end="24" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index cfae4a8b65..834f5773ff 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3406,6 +3406,32 @@
<field name="GAM Done" start="31" end="31" type="bool"/>
</register>
+ <register name="SC_INSTDONE" length="1" num="0x7100">
+ <field name="SVL Done" start="0" end="0" type="bool"/>
+ <field name="WMFE Done" start="1" end="1" type="bool"/>
+ <field name="WMBE Done" start="2" end="2" type="bool"/>
+ <field name="HIZ Done" start="3" end="3" type="bool"/>
+ <field name="STC Done" start="4" end="4" type="bool"/>
+ <field name="IZ Done" start="5" end="5" type="bool"/>
+ <field name="SBE Done" start="6" end="6" type="bool"/>
+ <field name="RCZ Done" start="8" end="8" type="bool"/>
+ <field name="RCC Done" start="9" end="9" type="bool"/>
+ <field name="RCPBE Done" start="10" end="10" type="bool"/>
+ <field name="RCPFE Done" start="11" end="11" type="bool"/>
+ <field name="DAPB Done" start="12" end="12" type="bool"/>
+ <field name="DAPRBE Done" start="13" end="13" type="bool"/>
+ <field name="SARB Done" start="15" end="15" type="bool"/>
+ <field name="DC0 Done" start="16" end="16" type="bool"/>
+ <field name="DC1 Done" start="17" end="17" type="bool"/>
+ <field name="DC2 Done" start="18" end="18" type="bool"/>
+ <field name="DC3 Done" start="19" end="19" type="bool"/>
+ <field name="GW0 Done" start="20" end="20" type="bool"/>
+ <field name="GW1 Done" start="21" end="21" type="bool"/>
+ <field name="GW2 Done" start="22" end="22" type="bool"/>
+ <field name="GW3 Done" start="23" end="23" type="bool"/>
+ <field name="TDC Done" start="24" end="24" type="bool"/>
+ </register>
+
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
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