Mesa (master): intel/compiler: lower some 16-bit integer operations to 32-bit

[Iago Toral Quiroga]

Module: Mesa
Branch: master
Commit: b11e9425df24f8c07a4cda85717407726f2d5330
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b11e9425df24f8c07a4cda85717407726f2d5330

Author: Iago Toral Quiroga <itoral at igalia.com>
Date:   Thu Apr 26 10:07:56 2018 +0200

intel/compiler: lower some 16-bit integer operations to 32-bit

These are not supported in hardware for 16-bit integers.

We do the lowering pass after the optimization loop to ensure that we
lower ALU operations injected by algebraic optimizations too.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

---

 src/intel/compiler/brw_nir.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 9998c59586..97d28db88e 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -592,6 +592,25 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
    return nir;
 }
 
+static unsigned
+lower_bit_size_callback(const nir_alu_instr *alu, void *data)
+{
+   assert(alu->dest.dest.is_ssa);
+   if (alu->dest.dest.ssa.bit_size != 16)
+      return 0;
+
+   switch (alu->op) {
+   case nir_op_idiv:
+   case nir_op_imod:
+   case nir_op_irem:
+   case nir_op_udiv:
+   case nir_op_umod:
+      return 32;
+   default:
+      return 0;
+   }
+}
+
 /* Does some simple lowering and runs the standard suite of optimizations
  *
  * This is intended to be called more-or-less directly after you get the
@@ -645,6 +664,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
 
    nir = brw_nir_optimize(nir, compiler, is_scalar);
 
+   nir_lower_bit_size(nir, lower_bit_size_callback, NULL);
+
    if (is_scalar) {
       OPT(nir_lower_load_const_to_scalar);
    }