Mesa (master): Revert "i965/compiler: handle conversion to smaller type in the lowering pass for that"

[Mark Janes]

Module: Mesa
Branch: master
Commit: 7b9c15628aae8729118b648f5f473e6ac926b99b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b9c15628aae8729118b648f5f473e6ac926b99b

Author: Mark Janes <mark.a.janes at intel.com>
Date:   Thu May  3 14:28:00 2018 -0700

Revert "i965/compiler: handle conversion to smaller type in the lowering pass for that"

This reverts commit 96b51537908cd2aace85f54b437eeb72e6346b7e.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

---

 src/intel/compiler/brw_fs_lower_conversions.cpp |  5 +----
 src/intel/compiler/brw_fs_nir.cpp               | 14 +++++++++++---
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/intel/compiler/brw_fs_lower_conversions.cpp b/src/intel/compiler/brw_fs_lower_conversions.cpp
index f95b39d3e8..663c9674c4 100644
--- a/src/intel/compiler/brw_fs_lower_conversions.cpp
+++ b/src/intel/compiler/brw_fs_lower_conversions.cpp
@@ -54,7 +54,7 @@ fs_visitor::lower_conversions()
       bool saturate = inst->saturate;
 
       if (supports_type_conversion(inst)) {
-         if (type_sz(inst->dst.type) < get_exec_type_size(inst)) {
+         if (get_exec_type_size(inst) == 8 && type_sz(inst->dst.type) < 8) {
             /* From the Broadwell PRM, 3D Media GPGPU, "Double Precision Float to
              * Single Precision Float":
              *
@@ -64,9 +64,6 @@ fs_visitor::lower_conversions()
              * So we need to allocate a temporary that's two registers, and then do
              * a strided MOV to get the lower DWord of every Qword that has the
              * result.
-             *
-             * This restriction applies, in general, whenever we convert to
-             * a type with a smaller bit-size.
              */
             fs_reg temp = ibld.vgrf(get_exec_type(inst));
             fs_reg strided_temp = subscript(temp, dst.type, 0);
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 4c8bcc4ebc..f9fde145a1 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -755,9 +755,19 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
        */
 
    case nir_op_f2f16_undef:
-      inst = bld.MOV(result, op[0]);
+   case nir_op_i2i16:
+   case nir_op_u2u16: {
+      /* TODO: Fixing aligment rules for conversions from 32-bits to
+       * 16-bit types should be moved to lower_conversions
+       */
+      fs_reg tmp = bld.vgrf(op[0].type, 1);
+      tmp = subscript(tmp, result.type, 0);
+      inst = bld.MOV(tmp, op[0]);
+      inst->saturate = instr->dest.saturate;
+      inst = bld.MOV(result, tmp);
       inst->saturate = instr->dest.saturate;
       break;
+   }
 
    case nir_op_f2f64:
    case nir_op_f2i64:
@@ -797,8 +807,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
    case nir_op_f2u16:
    case nir_op_i2i32:
    case nir_op_u2u32:
-   case nir_op_i2i16:
-   case nir_op_u2u16:
    case nir_op_i2f16:
    case nir_op_u2f16:
       inst = bld.MOV(result, op[0]);