Mesa (master): i965: require pixel scoreboard stall prior to ISP disable

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: f536097f67521180dafd270b28ac9a852af9c141
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f536097f67521180dafd270b28ac9a852af9c141

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Tue May  1 12:32:45 2018 +0100

i965: require pixel scoreboard stall prior to ISP disable

Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.

v2: Fix compile issue :(

v3: Stall on pixel scoreboard

v4: Drop the post sync operation (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243

---

 src/mesa/drivers/dri/i965/brw_pipe_control.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 02278be6d6..879bfb660e 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -349,14 +349,21 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
  * context restore, so the mentioned hang doesn't happen. However,
  * software must program push constant commands for all stages prior to
  * rendering anything, so we flag them as dirty.
+ *
+ * Finally, we also make sure to stall at pixel scoreboard to make sure the
+ * constants have been loaded into the EUs prior to disable the push constants
+ * so that it doesn't hang a previous 3DPRIMITIVE.
  */
 void
 gen10_emit_isp_disable(struct brw_context *brw)
 {
    brw_emit_pipe_control(brw,
-                         PIPE_CONTROL_ISP_DIS |
+                         PIPE_CONTROL_STALL_AT_SCOREBOARD |
                          PIPE_CONTROL_CS_STALL,
                          NULL, 0, 0);
+   brw_emit_pipe_control(brw,
+                         PIPE_CONTROL_ISP_DIS,
+                         NULL, 0, 0);
 
    brw->vs.base.push_constants_dirty = true;
    brw->tcs.base.push_constants_dirty = true;