Mesa (master): i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Thu May 10 01:03:49 UTC 2018
Module: Mesa
Branch: master
Commit: a8a740f272a808a2694524b43fc33d2f0c0e3709
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8a740f272a808a2694524b43fc33d2f0c0e3709
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 9 15:06:13 2018 -0700
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
>From the bspec docs for "Indirect State Pointers Disable":
"At the completion of the post-sync operation associated with this
pipe control packet, the indirect state pointers in the hardware are
considered invalid"
So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall. Without this, the simulator throws
an error.
Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
src/intel/vulkan/genX_cmd_buffer.c | 1 +
src/mesa/drivers/dri/i965/brw_pipe_control.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 526e18af10..afccad8ef8 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1434,6 +1434,7 @@ emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.IndirectStatePointersDisable = true;
+ pc.CommandStreamerStallEnable = true;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 879bfb660e..e31d625ddb 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -362,7 +362,8 @@ gen10_emit_isp_disable(struct brw_context *brw)
PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw_emit_pipe_control(brw,
- PIPE_CONTROL_ISP_DIS,
+ PIPE_CONTROL_ISP_DIS |
+ PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw->vs.base.push_constants_dirty = true;
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