Mesa (master): intel/fs: Assert that the gen4-6 plane restrictions are followed
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Tue May 29 22:45:33 UTC 2018
Module: Mesa
Branch: master
Commit: a1a850cd3411400ce832e77c4be1f0e14924ce9e
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1a850cd3411400ce832e77c4be1f0e14924ce9e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 16 17:30:04 2018 -0700
intel/fs: Assert that the gen4-6 plane restrictions are followed
The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
---
src/intel/compiler/brw_fs_generator.cpp | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 6d5306a0ee..0c050a73b4 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -817,8 +817,14 @@ fs_generator::generate_linterp(fs_inst *inst,
}
return true;
- } else if (devinfo->has_pln &&
- (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
+ } else if (devinfo->has_pln) {
+ /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
+ *
+ * "[DevSNB]:<src1> must be even register aligned.
+ *
+ * This restriction is lifted on Ivy Bridge.
+ */
+ assert(devinfo->gen >= 7 || (delta_x.nr & 1) == 0);
brw_PLN(p, dst, interp, delta_x);
return false;
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