Mesa (18.0): 27 new commits

Thu May 31 07:55:54 UTC 2018

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c644f48a1c57da6e14fcf2f3d484d5416fe7485
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Wed May 30 10:02:00 2018 +0200

    cherry-ignore: nv30: ensure that displayable formats are marked accordingly

    stable: Explicit 18.1 only nomination.

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfa3a7ee378009d65525613e68d4252040181c74
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Wed May 30 09:57:02 2018 +0200

    cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)

    stable: The commit requires earlier commit 19a91841c3 which did not land in branch.

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=81bd117b3cfbdd73181e44fbedb5e42c4c492406
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri May 25 16:37:29 2018 -0400

    mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)

    Bindless texture handles can be passed via vertex attribs using this type.
    This fixes a bunch of bindless piglit tests on radeonsi.

    Cc: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
    (cherry picked from commit a8e141387686cdf44b5868031283267acb99eba7)
    [Juan A. Suarez: resolve trivial conflict]
    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

    Conflicts:
    	src/mesa/vbo/vbo_private.h

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=714dabe3178fc141e2899ad58f421138b7fb2198
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Wed May 30 09:37:58 2018 +0200

    cherry-ignore: Tegra is not supported

    stable: Tegra support was not added in the current branch.

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aac580f7bb342c6acb4652a569154f4019b6d350
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 25 12:27:17 2018 -0700

    intel/blorp: Support blits and clears on surfaces with offsets

    For certain EGLImage cases, we represent a single slice or LOD of an
    image with a byte offset to a tile and X/Y intratile offsets to the
    given slice.  Most of i965 is fine with this but it breaks blorp.  This
    is a terrible way to represent slices of a surface in EGL and we should
    stop some day but that's a very scary and thorny path.  This gets blorp
    to start working with those surfaces and fixes some dEQP EGL test bugs.

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629
    Cc: mesa-stable at lists.freedesktop.org
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    (cherry picked from commit ae514ca695a599cdd0b7c22f48fd4d721671b0cb)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=38aeeee511f05c14ee51e20b4033a26372374976
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed May 23 00:16:25 2018 -0400

    radeonsi: fix incorrect parentheses around VS-PS varying elimination

    I don't know if it caused issues.

    Cc: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    (cherry picked from commit 92ea9329e5eacf9a44ed30b3d72038a411eb771a)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cf02769f59fc4e193dd81787d4f9d2e91d5d2ff
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed May 23 14:41:25 2018 -0400

    st/mesa: simplify lastLevel determination in st_finalize_texture

    This fixes shader images where we always bind stObj->pt and not individual
    gl_texture_images.

    Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308
    which does a similar thing but for a different reason.

    This fixes GL CTS assertion failures introduced by Ilia.

    Cc: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    (cherry picked from commit a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1939affe5181beb9674060d04c905c284f4a6e0a
Author: Jose Dapena Paz <jose.dapena at lge.com>
Date:   Thu May 24 19:56:24 2018 +0200

    mesa: do not leak ctx->Shader.ReferencedProgram references

    When glUseProgram is used, references to the included shaders are
    added in ctx->Shader.ReferencedProgram. But those references are not
    decreased when the shader data is deallocated. Thus, those shaders
    are leaked.

    Explicitely remove the pending references to these shaders.

    Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use")
    Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
    (cherry picked from commit 6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=42fa7cf2bb6a61897ac3dd701622955e52df2b75
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Mar 16 14:28:59 2018 -0700

    i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.

    Instead of directly using intel_obj->buffer.  Among other things
    intel_bufferobj_buffer() will update intel_buffer_object::
    gpu_active_start/end, which are used by glBufferSubData() to decide
    which path to take.  Fixes a failure in the Piglit
    ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests,
    which could be reproduced with a non-standard glGetTexSubImage
    implementation (see bug report).

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351
    Reported-by: Nanley Chery <nanleychery at gmail.com>
    Cc: mesa-stable at lists.freedesktop.org
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
    (cherry picked from commit 936cd3c87a212c28fe89a5c059fc4febd8b52ab7)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=86e749a96e480ef0ea82a94023d8e73966a30047
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Mar 16 14:35:10 2018 -0700

    i965: Handle non-zero texture buffer offsets in buffer object range calculation.

    Otherwise the specified surface state will allow the GPU to access
    memory up to BufferOffset bytes past the end of the buffer.  Found by
    inspection.

    v2: Protect against out-of-range BufferOffset (Nanley).
    Cc: mesa-stable at lists.freedesktop.org
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
    (cherry picked from commit e989acb03ba802737f762627dd16ac1d0b9f0d13)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=03eaee15298a3d24edbf23bdf9d7b1f8bbc2c8bb
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Mar 16 13:06:26 2018 -0700

    i965: Move buffer texture size calculation into a common helper function.

    The buffer texture size calculations (should be easy enough, right?)
    are repeated in three different places, each of them subtly broken in
    a different way.  E.g. the image load/store path was never fixed to
    clamp to MaxTextureBufferSize, and none of them are taking into
    account the buffer offset correctly.  It's easier to fix it all in one
    place.

    Cc: mesa-stable at lists.freedesktop.org
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
    (cherry picked from commit 156d2c6e621d836c4d45c636b87669e1de3d4464)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d5f09e8ef4a82a05c3f2d305e578cbd1cd3c9cd
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Mar 16 13:43:27 2018 -0700

    Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"

    This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145.  It was
    preventing the image format validation from being done on buffer
    textures, which is required to ensure that the application doesn't
    attempt to bind a buffer texture with an internal format incompatible
    with the image unit format (e.g. of different texel size), which is
    not allowed by the spec (it's not allowed for *any* texture target,
    whether or not there is spec wording restricting this behavior
    specifically for buffer textures) and will cause the driver to
    calculate texel bounds incorrectly and potentially crash instead of
    the expected behavior.

    Cc: mesa-stable at lists.freedesktop.org
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
    (cherry picked from commit 5a6814780322988a7adee525899bca8a83907ab7)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a93a86a434b34b2e1025c3962ffd26454f787c44
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 18 20:04:12 2018 -0700

    intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0

    Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
    Reviewed-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
    (cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a0c2860e7237badfd71d063fa3b91a4a25f595a
Author: Dave Airlie <airlied at redhat.com>
Date:   Thu May 10 01:01:58 2018 +0100

    tgsi/scan: add hw atomic to the list of memory accessing files

    This fixes 4 out of 5 cases in:
    arb_framebuffer_no_attachments-atomic on cayman.

    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Cc: "18.0 18.1" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit f2f464de576187891eeadb3e7fadf9ddbf322cba)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b582b8fc93697d193365bf11cd9f336d786d7f8d
Author: Michel Dänzer <michel.daenzer at amd.com>
Date:   Tue May 8 11:51:09 2018 +0200

    dri3: Stricter SBC wraparound handling

    Prevents corrupting the upper 32 bits of draw->recv_sbc when
    draw->send_sbc resets to 0 (which currently happens when the window is
    unbound from a context and bound to one again), which in turn caused
    loader_dri3_swap_buffers_msc to calculate target_msc with corrupted
    upper 32 bits. This resulted in hangs with the Xorg modesetting driver
    as of xserver 1.20 (older versions and other drivers ignored the upper
    32 bits of the target MSC, which is why this wasn't noticed earlier).

    Cc: mesa-stable at lists.freedesktop.org
    Bugzilla: https://bugs.freedesktop.org/106351
    Tested-by: Mike Lothian <mike at fireburn.co.uk>
    (cherry picked from commit fe2edb25dd5628c395a65b60998f11e839d2b458)
    [Juan A. Suarez: resolve trivial conflicts]

    Conflicts:
    	src/loader/loader_dri3_helper.c

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96b1ac39d58dedf7ed7dbc9dac5116783bb9c2e4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon May 21 11:15:51 2018 +0200

    radv: fix centroid interpolation

    It's legal to set the centroid and sample interpolation modes
    when MSAA disabled. So, we have to initialize the centroid
    inputs because the hardware doesn't.

    This fixes rendering issues with DXVK and The Witness, World of
    Warcraft, Trackmania and probably more games.

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390
    CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    (cherry picked from commit 73df16dcee79e2281c8d8a830dbbe6655359c82d)
    [Juan A. Suarez: apply change in src/amd/common/ac_nir_to_llvm.c]
    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

    Conflicts:
    	src/amd/vulkan/radv_nir_to_llvm.c

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f844591ee358a2ee9fa9fe9804743d59e7f465b0
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Mon May 21 15:21:56 2018 -0700

    i965/glk: Add l3 banks count for 2x6 configuration

    2x6 configuration with pci-id 0x3185 has same number of
    banks (2) as 3x6 configuration (pci-id 0x3184).

    Reported-by: Clayton Craft <clayton.a.craft at intel.com>
    Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
    Tested-by: Clayton Craft <clayton.a.craft at intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+"
    Cc: Francisco Jerez <currojerez at riseup.net>
    (cherry picked from commit 0748383a6014886ef0bf7bda16fd0efef39c405d)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=620be4d431c1151a5a675dc8a361c2aaac6f3831
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date:   Thu May 10 13:42:16 2018 +1000

    mesa: add glUniform*ui{v} support to display lists

    Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms"

    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097
    (cherry picked from commit f71714022b2cd26bb1892e6a7f3d7308515f210e)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5443d858702f892f54033fae382f7e865af7b1f1
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Tue May 22 12:26:08 2018 +0200

    cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too

    fixes: The commit fixes earlier commits 19a91841c3 and 9987a072cb which
    did not land in branch.

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cef37e9095fc55d3a88f3f01d97c8f84d20edfc
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Mon May 21 01:26:46 2018 +0200

    radv: Fix SRGB compute copies.

    SRGB stores are broken. We had compensation code in the
    resolve path but none in the copy path. Since we don't
    want any conversion and it does not matter for DCC,
    just make everything UNORM instead.

    This happened to cause wrong colors for the PRIME path, as
    that uses image->buffer copies which always use the compute
    path.

    CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587
    Reviewed-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit a63a0960e3ebf049e593f51ce1e02dc84254f9c4)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7b5064045f8b133059e8948a5871b755ca5ce9b
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Tue May 22 12:00:40 2018 +0200

    cherry-ignore: add explicit 18.1 only nominations

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ce8a775a75ed1e9960ca32a7f0d47e04529a729
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Mon May 14 17:38:36 2018 +0200

    amd/addrlib: Use defines in autotools build.

    Otherwise stuff like NDEBUG would not be passed through.

    CC: <mesa-stable at lists.freedesktop.org>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    (cherry picked from commit 62e0e089d710835d9f79138377bcc37147f75ebd)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b7134c5350df5fcc04b71d9598154bbc6451256
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed May 2 09:38:47 2018 -0700

    i965/miptree: Zero-initialize CCS_D buffers

    Before this patch, the aux_state was actually AUX_INVALID because the BO
    was never defined. This was fine on single slice miptrees because we
    would fast-clear the resource right after creation. For multi-slice
    miptrees on SKL+ however, this results in undefined behavior when
    accessing a non-base slice. Here's a specific example:

    1) Fast clear level 0
       * Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
       * Level 0 transitions to the CLEAR state.
    2) Render to level 1
       * Level 1 may have a 2-bit pattern of 2's.
       * Rendering with a 2 in the CCS is undefined.

    Cc: <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    (cherry picked from commit 8a9491058da72ee2df75da25bb147010a451fb68)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

    Conflicts:
    	src/mesa/drivers/dri/i965/intel_mipmap_tree.c

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=544a3838584289a8f2b6d9c43cb0348e26b769cb
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Tue May 22 11:46:37 2018 +0200

    cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers

    stable: The commit requires earlier commit af4e9295fe which did not land
    in branch.

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f084db88702a8e5bbfa460dfb9d6e9bf422554ae
Author: Stuart Young <cefiar at gmail.com>
Date:   Thu May 17 03:01:43 2018 +1000

    etnaviv: Fix missing rnndb file in tarballs

    Seems that when the rnndb files for etniviv were updated/included back
    in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
    meson.build. This was all during the conversion to meson, so it apears
    to have slipped through the cracks. As such, this file has been missing
    from the official tarballs since inclusion in Mesa, so the git trees
    and tarballs differ.

    Found due to lintian errors in the Debian packages.

    Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")
    Cc: mesa-stable at lists.freedesktop.org
    Reviewed-by: Christian Gmeiner <christian.gmeiner at gmail.com>
    (cherry picked from commit f806cc9eb6be1a84a9987b142e7fce1ec2cb7973)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=712456cb388403955b30fa544b6858d7a4aa8cce
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date:   Thu May 3 19:26:29 2018 -0400

    eg/compute: Use reference counting to handle compute memory pool.

    Use pipe_reference to release old RAT surfaces.
    RAT surface adds a reference to pool bo, so use reference counting for pool->bo
    as well.

    v2: Use the same pattern for both defrag paths
        Drop confusing comment

    CC: <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
    Reviewed-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit f3521ce2c440bd50020a3ff81e6d9fa17c01009c)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f7b29aa93004bcfc1e6461d0823bf1da941ccce
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue May 15 12:00:30 2018 +0200

    spirv: fix visiting inner loops with same break/continue block

    We should stop walking through the CFG when the inner loop's
    break block ends up as the same block as the outer loop's
    continue block because we are already going to visit it.

    This fixes the following assertion which ends up by crashing
    in RADV or ANV:

    SPIR-V parsing FAILED:
    In file ../src/compiler/spirv/vtn_cfg.c:381
    block->node.link.next == NULL
    0 bytes into the SPIR-V binary

    This also fixes a crash with a camera shader from SteamVR.

    v2: make use of vtn_get_branch_type() and add an assertion

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504
    CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    (cherry picked from commit 6bde8c560877512852ff49fafa296eb71a5ec14b)