Mesa (18.1): 40 new commits
Dylan Baker
dbaker at kemper.freedesktop.org
Thu May 31 17:16:51 UTC 2018
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3897b667a06ea5c3760b1acc974847be035476b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri May 25 16:37:29 2018 -0400
mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)
Bindless texture handles can be passed via vertex attribs using this type.
This fixes a bunch of bindless piglit tests on radeonsi.
Cc: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
(cherry picked from commit a8e141387686cdf44b5868031283267acb99eba7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=df303adc29e580f3eb27e5e787387dfe98aaa56f
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri May 18 17:12:53 2018 +0100
vulkan: don't free uninitialised memory
The modifiers array hasn't been initialised by then, much less with data
that would need freeing.
Move the label after the loop to fix this.
Fixes: c80c08e22603 ("vulkan/wsi/x11: Add support for DRI3 v1.2")
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(cherry picked from commit e4fe2fd3bb26d52e64d98207692a4469f04fe1d5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6167e9640664b22d025813fb4061c91aae2af8c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 28 11:07:08 2018 -0400
nv30: ensure that displayable formats are marked accordingly
Fixes: f7604d8af52 ("st/dri: only expose config formats that are display targets")
Cc: "18.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
(cherry picked from commit 30918b77ac82ba1da7764c0375233656e0ebf9f9)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55de9df50e93b4e2bc6792b5753565f070459696
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed May 30 08:50:03 2018 +0200
radv: Only expose subgroup shuffles on VI+.
The current implementation depends on bpermute, which
is VI+.
Fixes: f2c6a550611 "radv: enable subgroup capabilities"
Reviewed-by: Daniel Schürmann <daniel.schuermann at campus.tu-berlin.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit c2799574eb104218ac4f6b8a3d64b8a0f8c89525)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5015436eaf707ba208b8eccde853857c0686ffa4
Author: Thierry Reding <treding at nvidia.com>
Date: Mon Mar 12 17:53:51 2018 +0100
tegra: Remove usage of non-stable UAPI
This code path is no longer required with framebuffer modifier support.
Tested-by: Daniel Kolesa <daniel at octaforge.org>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Thierry Reding <treding at nvidia.com>
(cherry picked from commit bd3e97e5aad7800b8e17ed10d34a070926691945)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=92c633881e0560fd9862423aa55691eb049b19c7
Author: Thierry Reding <treding at nvidia.com>
Date: Thu Mar 15 21:59:02 2018 +0100
tegra: Fix scanout resources without modifiers
Resources created for scanout but without modifiers need to be treated
as pitch-linear. This is because applications that don't use modifiers
to create resources must be assumed to not understand modifiers and in
turn won't be able to create a DRM framebuffer and passing along which
modifiers were picked by the implementation.
Tested-by: Daniel Kolesa <daniel at octaforge.org>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Thierry Reding <treding at nvidia.com>
(cherry picked from commit 9603d81df05105857b676f20dff964ef3ab0ecff)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b8f87cefe72174af67a18c063494f70120e3bf4
Author: Thierry Reding <treding at nvidia.com>
Date: Wed Apr 4 16:04:25 2018 +0200
tegra: Treat resources with modifiers as scanout
Resources created with modifiers are treated as scanout because there is
no way for applications to specify the usage (though that capability may
be useful to have in the future). Currently all the resources created by
applications with modifiers are for scanout, so make sure they have bind
flags set accordingly.
This is necessary in order to properly export buffers for such resources
so that they can be shared with scanout hardware.
Tested-by: Daniel Kolesa <daniel at octaforge.org>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Thierry Reding <treding at nvidia.com>
(cherry picked from commit 9e539012dfaa848fc4cfde83c3f3a83fee274ca4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dd9532d158121c3023a2ba53be9d3f290c4157b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri May 25 12:27:17 2018 -0700
intel/blorp: Support blits and clears on surfaces with offsets
For certain EGLImage cases, we represent a single slice or LOD of an
image with a byte offset to a tile and X/Y intratile offsets to the
given slice. Most of i965 is fine with this but it breaks blorp. This
is a terrible way to represent slices of a surface in EGL and we should
stop some day but that's a very scary and thorny path. This gets blorp
to start working with those surfaces and fixes some dEQP EGL test bugs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit ae514ca695a599cdd0b7c22f48fd4d721671b0cb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36e65cc47fe7829fa1177cc7763190ef82493400
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 23 00:16:25 2018 -0400
radeonsi: fix incorrect parentheses around VS-PS varying elimination
I don't know if it caused issues.
Cc: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
(cherry picked from commit 92ea9329e5eacf9a44ed30b3d72038a411eb771a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cb16ce7e9a6886f0e77942f794b3e223657a1ba
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 23 14:41:25 2018 -0400
st/mesa: simplify lastLevel determination in st_finalize_texture
This fixes shader images where we always bind stObj->pt and not individual
gl_texture_images.
Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308
which does a similar thing but for a different reason.
This fixes GL CTS assertion failures introduced by Ilia.
Cc: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
(cherry picked from commit a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b588bf361f80a00591d60319a3c0d0fce7d6f4f
Author: Jose Dapena Paz <jose.dapena at lge.com>
Date: Thu May 24 19:56:24 2018 +0200
mesa: do not leak ctx->Shader.ReferencedProgram references
When glUseProgram is used, references to the included shaders are
added in ctx->Shader.ReferencedProgram. But those references are not
decreased when the shader data is deallocated. Thus, those shaders
are leaked.
Explicitely remove the pending references to these shaders.
Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use")
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
(cherry picked from commit 6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54ff500546ccfc976c904a8f19d3330d93eff6ab
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Mar 16 14:28:59 2018 -0700
i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.
Instead of directly using intel_obj->buffer. Among other things
intel_bufferobj_buffer() will update intel_buffer_object::
gpu_active_start/end, which are used by glBufferSubData() to decide
which path to take. Fixes a failure in the Piglit
ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests,
which could be reproduced with a non-standard glGetTexSubImage
implementation (see bug report).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351
Reported-by: Nanley Chery <nanleychery at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
(cherry picked from commit 936cd3c87a212c28fe89a5c059fc4febd8b52ab7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c1ab9609cf4506684d533a967e4694c9be7873e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Mar 16 14:35:10 2018 -0700
i965: Handle non-zero texture buffer offsets in buffer object range calculation.
Otherwise the specified surface state will allow the GPU to access
memory up to BufferOffset bytes past the end of the buffer. Found by
inspection.
v2: Protect against out-of-range BufferOffset (Nanley).
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
(cherry picked from commit e989acb03ba802737f762627dd16ac1d0b9f0d13)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b5f4fca95203d2ff1374763912ab54869701142
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Mar 16 13:06:26 2018 -0700
i965: Move buffer texture size calculation into a common helper function.
The buffer texture size calculations (should be easy enough, right?)
are repeated in three different places, each of them subtly broken in
a different way. E.g. the image load/store path was never fixed to
clamp to MaxTextureBufferSize, and none of them are taking into
account the buffer offset correctly. It's easier to fix it all in one
place.
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
(cherry picked from commit 156d2c6e621d836c4d45c636b87669e1de3d4464)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d795a1a691de5b8ff711d6b8073c1dd1c02c4adc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Mar 16 13:43:27 2018 -0700
Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"
This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145. It was
preventing the image format validation from being done on buffer
textures, which is required to ensure that the application doesn't
attempt to bind a buffer texture with an internal format incompatible
with the image unit format (e.g. of different texel size), which is
not allowed by the spec (it's not allowed for *any* texture target,
whether or not there is spec wording restricting this behavior
specifically for buffer textures) and will cause the driver to
calculate texel bounds incorrectly and potentially crash instead of
the expected behavior.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
(cherry picked from commit 5a6814780322988a7adee525899bca8a83907ab7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7366a91340578d5627a00eb39cb7273e38164ba8
Author: Dave Airlie <airlied at redhat.com>
Date: Thu May 10 01:01:58 2018 +0100
tgsi/scan: add hw atomic to the list of memory accessing files
This fixes 4 out of 5 cases in:
arb_framebuffer_no_attachments-atomic on cayman.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "18.0 18.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit f2f464de576187891eeadb3e7fadf9ddbf322cba)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4b86e96e8e9195e4a4671b547d79d7cafe41467
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Tue May 8 11:51:09 2018 +0200
dri3: Stricter SBC wraparound handling
Prevents corrupting the upper 32 bits of draw->recv_sbc when
draw->send_sbc resets to 0 (which currently happens when the window is
unbound from a context and bound to one again), which in turn caused
loader_dri3_swap_buffers_msc to calculate target_msc with corrupted
upper 32 bits. This resulted in hangs with the Xorg modesetting driver
as of xserver 1.20 (older versions and other drivers ignored the upper
32 bits of the target MSC, which is why this wasn't noticed earlier).
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/106351
Tested-by: Mike Lothian <mike at fireburn.co.uk>
(cherry picked from commit fe2edb25dd5628c395a65b60998f11e839d2b458)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=14689dccbfaf11e5b83aeb971155c77cbc486477
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri May 18 20:04:12 2018 -0700
intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
(cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66604a75181f52d1fc64d09757f364f200ef566b
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon May 21 15:21:56 2018 -0700
i965/glk: Add l3 banks count for 2x6 configuration
2x6 configuration with pci-id 0x3185 has same number of
banks (2) as 3x6 configuration (pci-id 0x3184).
Reported-by: Clayton Craft <clayton.a.craft at intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Tested-by: Clayton Craft <clayton.a.craft at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+"
Cc: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit 0748383a6014886ef0bf7bda16fd0efef39c405d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd18f81a0cc925ddc68da48c6551b7cfb8273a31
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon May 21 11:15:51 2018 +0200
radv: fix centroid interpolation
It's legal to set the centroid and sample interpolation modes
when MSAA disabled. So, we have to initialize the centroid
inputs because the hardware doesn't.
This fixes rendering issues with DXVK and The Witness, World of
Warcraft, Trackmania and probably more games.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390
CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 73df16dcee79e2281c8d8a830dbbe6655359c82d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b49daeac88f2a66e63c5a692ca06299442dd4c3f
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Mon May 21 01:26:46 2018 +0200
radv: Fix SRGB compute copies.
SRGB stores are broken. We had compensation code in the
resolve path but none in the copy path. Since we don't
want any conversion and it does not matter for DCC,
just make everything UNORM instead.
This happened to cause wrong colors for the PRIME path, as
that uses image->buffer copies which always use the compute
path.
CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587
Reviewed-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit a63a0960e3ebf049e593f51ce1e02dc84254f9c4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f969afdf2debb44ade50e35baef5f7f7e134b317
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Mon May 14 17:38:36 2018 +0200
amd/addrlib: Use defines in autotools build.
Otherwise stuff like NDEBUG would not be passed through.
CC: <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 62e0e089d710835d9f79138377bcc37147f75ebd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d4b5b0745ba37290bd164e3e56f94650850b70d
Author: Dave Airlie <airlied at redhat.com>
Date: Fri May 18 10:44:27 2018 +1000
virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.
The host side hasn't got support for this feature yet, so don't enable it
unless we get the caps from the host.
This makes the texture buffer range piglit tests skip now.
Fixes: fe0647df5a7 (virgl: add offset alignment values to to v2 caps struct)
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
(cherry picked from commit bfa74bb44ddf3e81dedf9af28f86110dfd47dc45)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b79bbe27dc99f8bf12f82ca004f2f3f3cff25d6
Author: Christoph Haag <haagch at frickel.club>
Date: Sun May 20 13:21:13 2018 +0200
radv: fix VK_EXT_descriptor_indexing
GetPhysicalDeviceProperties2KHR() was crashing because features was null
Fixes: 0e10790558b "radv: Enable VK_EXT_descriptor_indexing."
CC: 18.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 549e54270ba3a519b46a1fbffa4aa6b628a052d3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fe826ee06d947734c3a847eb7495f368b70badb
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed May 2 09:38:47 2018 -0700
i965/miptree: Zero-initialize CCS_D buffers
Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base slice. Here's a specific example:
1) Fast clear level 0
* Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
* Level 0 transitions to the CLEAR state.
2) Render to level 1
* Level 1 may have a 2-bit pattern of 2's.
* Rendering with a 2 in the CCS is undefined.
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 8a9491058da72ee2df75da25bb147010a451fb68)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66fa6eceb9bea83b1428c2c36c983b3c0d60c22e
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Apr 30 10:40:18 2018 -0700
i965/miptree: Fix handling of uninitialized MCS buffers
Before this patch, if we failed to initialize an MCS buffer, we'd
end up in a state in which the miptree thinks it has an MCS buffer,
but doesn't. We also leaked the clear_color_bo if it existed.
With this patch, we now free the miptree aux buffer resources and let
intel_miptree_alloc_mcs() know that the MCS buffer no longer exists.
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 816f2dc67da72be8993e724aeda4c2ec2f5a2978)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21d51b4cea081b4828410de6e6e617c3a544e701
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Apr 6 09:54:31 2018 -0700
i965: Add and use a single miptree aux_buf field
We want to add and use a function that accesses the auxiliary buffer's
clear_color_bo and doesn't care if it has an MCS or HiZ buffer
specifically.
v2 (Jason Ekstrand):
* Drop intel_miptree_get_aux_buffer().
* Mention CCS in the aux_buf field.
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit af4e9295febe966ace7793e43ba35705521749e8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db4e345047c95bf0894fddfcfacdf52909221332
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Apr 9 11:11:46 2018 -0700
i965: Add and use a getter for the miptree aux buffer
Make the next patch easier to read by eliminating most of the would-be
duplicate field accesses now.
v2: Update the HiZ comment instead of deleting it (Rafael).
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
(cherry picked from commit 5503b65103b6a93dabe609cbedbbc999dd63bff5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9074b3c525baceccd8888ac0f99c9fcdf783b7e
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu May 10 13:42:16 2018 +1000
mesa: add glUniform*ui{v} support to display lists
Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms"
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097
(cherry picked from commit f71714022b2cd26bb1892e6a7f3d7308515f210e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4978181fdf6a903975c3caaa82c66659060ad211
Author: Stuart Young <cefiar at gmail.com>
Date: Thu May 17 03:01:43 2018 +1000
etnaviv: Fix missing rnndb file in tarballs
Seems that when the rnndb files for etniviv were updated/included back
in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
meson.build. This was all during the conversion to meson, so it apears
to have slipped through the cracks. As such, this file has been missing
from the official tarballs since inclusion in Mesa, so the git trees
and tarballs differ.
Found due to lintian errors in the Debian packages.
Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Christian Gmeiner <christian.gmeiner at gmail.com>
(cherry picked from commit f806cc9eb6be1a84a9987b142e7fce1ec2cb7973)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac152cb1f9b4c51a70c1a81cc678183328fabbc1
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date: Thu May 3 19:26:29 2018 -0400
eg/compute: Use reference counting to handle compute memory pool.
Use pipe_reference to release old RAT surfaces.
RAT surface adds a reference to pool bo, so use reference counting for pool->bo
as well.
v2: Use the same pattern for both defrag paths
Drop confusing comment
CC: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit f3521ce2c440bd50020a3ff81e6d9fa17c01009c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16591feedd687a88192fcec0ad13df6462bc0841
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue May 15 12:00:30 2018 +0200
spirv: fix visiting inner loops with same break/continue block
We should stop walking through the CFG when the inner loop's
break block ends up as the same block as the outer loop's
continue block because we are already going to visit it.
This fixes the following assertion which ends up by crashing
in RADV or ANV:
SPIR-V parsing FAILED:
In file ../src/compiler/spirv/vtn_cfg.c:381
block->node.link.next == NULL
0 bytes into the SPIR-V binary
This also fixes a crash with a camera shader from SteamVR.
v2: make use of vtn_get_branch_type() and add an assertion
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504
CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 6bde8c560877512852ff49fafa296eb71a5ec14b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=30e5b42fb9e89d8b0f12cbe9c76d0b2862c834ec
Author: Kai Wasserbäch <kai at dev.carbon-project.org>
Date: Tue May 1 14:14:46 2018 +0200
opencl: autotools: Fix linking order for OpenCL target
Otherwise the build fails with an undefined reference to
clang::FrontendTimesIsEnabled.
Bugzilla: https://bugs.freedesktop.org/106209
Cc: Jan Vesely <jan.vesely at rutgers.edu>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Acked-by: Jan Vesely <jan.vesely at rutgers.edu>
Tested-by: Aaron Watry <awatry at gmail.com>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
(cherry picked from commit b691d9192c436aba5a76577b7d772a791283a2e2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=287b28693152689434de2c2f1000c47d72d6601c
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat May 12 23:56:56 2018 +0200
radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.
The hardware always interprets the alpha as unsigned and fixing it
in the shader is going to add unacceptable overheads.
CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit f944a59996287de85d4c6d9b7b000d25f41b1d79)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d321533b2248dd64b3710d62e8634d945260985
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat May 12 23:50:04 2018 +0200
radv: Fix up 2_10_10_10 alpha sign.
Pre-Vega HW always interprets the alpha for this format as unsigned,
so we have to implement a fixup to do the sign correctly for signed
formats.
v2: Improve indexing mess.
CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 3d4d388e3929d7948b62d90867357aecbfba5aeb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15e7f80cf90be9017080aeab233131a7ca4acb5e
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Mon May 14 03:01:21 2018 +0200
radv: Translate logic ops.
radeonsi could pass them through but the enum changed between
Gallium and Vulkan, so we have to translate.
In progress I made the register defines a bit more readable.
CC: 18.0 18.1 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit dd102405dea022f6c27bc42176f50f3bb2761ae6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8a82e13f5f083a7828d02b235ea91509e8c3792
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sun May 13 22:01:44 2018 +0200
radv: Fix multiview queries.
This moves the extra queries to after the main query ended, instead
of doing it after the begin and hence doing nesting.
We also emit only (view count - 1) extra queries, as the main query
is already there for the first view.
This fixes the CTS occasionally getting stuck in
dEQP-VK.multiview.queries* waiting on results.
Fixes: 32b4f3c38dc "radv/query: handle multiview queries properly. (v3)"
CC: 18.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 62f50df7b79c273a0eb9bf769eded76933bddc3a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ea288d58401e52179d4339e3d25ff70dd7528be
Author: Dave Airlie <airlied at redhat.com>
Date: Fri May 11 14:55:29 2018 +1000
radv: use compute path for multi-layer images.
I don't think the hw resolve path can't handle multi-layer images.
This fixes all the:
dEQP-VK.renderpass.multisample_resolve.layers_*
tests on my VI card.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 5978d54a09e6ad151c0bd365de0e2c82bbf493d1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=73b78286830070b133484005576b902061ec63ce
Author: Dave Airlie <airlied at redhat.com>
Date: Fri May 11 14:54:21 2018 +1000
radv: resolve all layers in compute resolve path.
This path should iterate across all layers, I've some ideas
for doing this in a single pass, but this is simpler for now.
This passes the tests because we don't use the fragment path
unless we have DCC, and we don't have DCC on layered images.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 98dbaa445a83108b59bd56e8f3224c13c36ba1d5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3ac3fea3254fc1fe0b67516e5e5eaaf1184ad65
Author: Dave Airlie <airlied at redhat.com>
Date: Fri May 11 14:53:28 2018 +1000
radv/resolve: do fmask decompress on all layers.
For a multi-layer subpass resolve we want to make sure we flush all
the layers.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit b16fc6cda11576a4dd6c8d95f7bee94121c4b8e7)
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