Mesa (master): radv: set PA.SC_CONSERVATIVE_RASTERIZATION.NULL_SQUAD_AA_MASK_ENABLE

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Module: Mesa
Branch: master
Commit: f70c5d31cdfc64e5abdcd24e0f530c600534fa3d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f70c5d31cdfc64e5abdcd24e0f530c600534fa3d

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Nov 12 21:59:29 2018 +0100

radv: set PA.SC_CONSERVATIVE_RASTERIZATION.NULL_SQUAD_AA_MASK_ENABLE

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_pipeline.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f999383018..a126c03607 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2701,7 +2701,7 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
 	const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
 	const VkConservativeRasterizationModeEXT mode =
 		radv_get_conservative_raster_mode(vkraster);
-	uint32_t pa_sc_conservative_rast = 0;
+	uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
 
 	radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
 	                       S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.