Mesa (master): nir/spirv: cast shift operand to u32

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Module: Mesa
Branch: master
Commit: b4380cb070c0865f1fbfb3720056545665759bc3
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4380cb070c0865f1fbfb3720056545665759bc3

Author: Karol Herbst <kherbst at redhat.com>
Date:   Thu Apr 26 16:54:26 2018 +0200

nir/spirv: cast shift operand to u32

v2: fix for specialization constants as well

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Karol Herbst <kherbst at redhat.com>

---

 src/compiler/spirv/spirv_to_nir.c | 20 ++++++++++++++++++++
 src/compiler/spirv/vtn_alu.c      | 11 +++++++++++
 2 files changed, 31 insertions(+)

diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 96ff09c365..77ce0be369 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1811,6 +1811,26 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
             src[j] = src_val->constant->values[0];
          }
 
+         /* fix up fixed size sources */
+         switch (op) {
+         case nir_op_ishl:
+         case nir_op_ishr:
+         case nir_op_ushr: {
+            if (bit_size == 32)
+               break;
+            for (unsigned i = 0; i < num_components; ++i) {
+               switch (bit_size) {
+               case 64: src[1].u32[i] = src[1].u64[i]; break;
+               case 16: src[1].u32[i] = src[1].u16[i]; break;
+               case  8: src[1].u32[i] = src[1].u8[i];  break;
+               }
+            }
+            break;
+         }
+         default:
+            break;
+         }
+
          val->constant->values[0] =
             nir_eval_const_opcode(op, num_components, bit_size, src);
          break;
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 6860e7dc09..a23f8c29b5 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -696,6 +696,17 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
          src[1] = tmp;
       }
 
+      switch (op) {
+      case nir_op_ishl:
+      case nir_op_ishr:
+      case nir_op_ushr:
+         if (src[1]->bit_size != 32)
+            src[1] = nir_u2u32(&b->nb, src[1]);
+         break;
+      default:
+         break;
+      }
+
       val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]);
       break;
    } /* default */