Mesa (staging/18.2): anv: Put robust buffer access in the pipeline hash

[GitLab Mirror]

Module: Mesa
Branch: staging/18.2
Commit: 35379ec233353d19d94994dfa43b205a6b5622b2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=35379ec233353d19d94994dfa43b205a6b5622b2

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Nov 21 17:15:37 2018 -0600

anv: Put robust buffer access in the pipeline hash

It affects apply_pipeline_layout.  Shaders compiled with the wrong value
will work but they may not be robust as requested by the app.

Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
(cherry picked from commit 617e402b3d1be185f200b1667540096d9a8b2aec)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

Conflicts:
	src/intel/vulkan/anv_pipeline.c

---

 src/intel/vulkan/anv_pipeline.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 0770602552..184a2383d8 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -411,6 +411,8 @@ anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
    }
    if (layout)
       _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
+   const bool rba = pipeline->device->robust_buffer_access;
+   _mesa_sha1_update(&ctx, &rba, sizeof(rba));
    _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
    _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
    _mesa_sha1_update(&ctx, &stage, sizeof(stage));