Mesa (master): i965/icl: Fix L3 configurations
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Mon Nov 26 23:13:19 UTC 2018
Module: Mesa
Branch: master
Commit: 3282c7be899f34cd6d2fe695976383c949e1c6c2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3282c7be899f34cd6d2fe695976383c949e1c6c2
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Oct 2 04:28:10 2018 -0700
i965/icl: Fix L3 configurations
Use L3 configuration specified in h/w specification.
V2: Drop configs which do under allocation of l3 cache.
Bump up the comment above table.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
---
src/intel/common/gen_l3_config.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index b977c6ab13..32264394fb 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -134,15 +134,15 @@ static const struct gen_l3_config cnl_l3_configs[] = {
/**
* ICL validated L3 configurations. \sa icl_l3_configs.
+ * Zeroth entry in below table has been commented out intentionally
+ * due to known issues with this configuration. Many other entries
+ * suggested by h/w specification aren't added here because they
+ * do under allocation of L3 cache with below partitioning.
*/
static const struct gen_l3_config icl_l3_configs[] = {
/* SLM URB ALL DC RO IS C T */
- {{ 0, 64, 64, 0, 0, 0, 0, 0 }},
- {{ 0, 64, 0, 16, 48, 0, 0, 0 }},
- {{ 0, 48, 0, 16, 64, 0, 0, 0 }},
- {{ 0, 32, 0, 0, 96, 0, 0, 0 }},
- {{ 0, 32, 96, 0, 0, 0, 0, 0 }},
- {{ 0, 32, 0, 16, 80, 0, 0, 0 }},
+ /*{{ 0, 16, 80, 0, 0, 0, 0, 0 }},*/
+ {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
{{ 0 }}
};
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