Mesa (master): radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK

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Module: Mesa
Branch: master
Commit: b38228ccb0e3a0874e8845a325a6b658bc2661ed
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b38228ccb0e3a0874e8845a325a6b658bc2661ed

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Wed Oct  3 16:09:24 2018 +0200

radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK

It has probably no effect without out of order rasterization
anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_pipeline.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 6b3e120802..2db44cb24f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1081,6 +1081,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 	ms->pa_sc_mode_cntl_1 =
 		S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
 		S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
+		S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
 		/* always 1: */
 		S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
 		S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
@@ -1124,8 +1125,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 	}
 
 	if (out_of_order_rast) {
-		ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
-					 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
+		ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1);
 	}
 
 	if (vkms && vkms->pSampleMask) {