Mesa (master): anv: Clear WM_HZ_OP overrides in init_device_state

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Module: Mesa
Branch: master
Commit: 0ee0e0b6b94bf2b7041da59b67220234f605ae60
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ee0e0b6b94bf2b7041da59b67220234f605ae60

Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Oct 11 16:31:08 2018 -0700

anv: Clear WM_HZ_OP overrides in init_device_state

This is basically a port of commit,
3ade766684933ac84e41634429fb693f85353c11
("i965: Disable 3DSTATE_WM_HZ_OP fields.")

The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in
the section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
Clear." It mentions that the packet overrides GPU state for the clear
operation and needs to be reset to 0s to clear the overrides. Depending
on the kernel, we may not get a context with the GPU state for this
packet zeroed. Do it ourselves just in case.

Prevents a number of GPU hangs when running crucible on ICL. I tried to
get the exact number of hangs that occurs without this patch, but was
unsuccessful. The test machine became unresponsive before completing the
full run.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/intel/vulkan/genX_state.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 75bcd96d78..42800a2581 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -157,6 +157,16 @@ genX(init_device_state)(struct anv_device *device)
       GEN_SAMPLE_POS_16X(sp._16xSample);
 #endif
    }
+
+   /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
+    * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
+    * Clear." It mentions that the packet overrides GPU state for the clear
+    * operation and needs to be reset to 0s to clear the overrides. Depending
+    * on the kernel, we may not get a context with the state for this packet
+    * zeroed. Do it ourselves just in case. We've observed this to prevent a
+    * number of GPU hangs on ICL.
+    */
+   anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 #endif
 
 #if GEN_GEN == 10