Mesa (master): radeonsi: set PA_SU_PRIM_FILTER_CNTL optimally
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Tue Oct 16 22:58:08 UTC 2018
Module: Mesa
Branch: master
Commit: b94824c787ba747060f359391ddf454a15843e63
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b94824c787ba747060f359391ddf454a15843e63
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Sep 28 20:16:13 2018 -0400
radeonsi: set PA_SU_PRIM_FILTER_CNTL optimally
---
src/gallium/drivers/radeonsi/si_gfx_cs.c | 1 +
src/gallium/drivers/radeonsi/si_state.c | 15 +++++++++++----
src/gallium/drivers/radeonsi/si_state.h | 1 +
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 84f5e4c872..474ffb547a 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -339,6 +339,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index babd171cbd..132085a40c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3242,6 +3242,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
static void si_emit_msaa_sample_locs(struct si_context *sctx)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
+ struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned nr_samples = sctx->framebuffer.nr_samples;
bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
@@ -3263,7 +3264,6 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx)
}
if (sctx->family >= CHIP_POLARIS10) {
- struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned small_prim_filter_cntl =
S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
/* line bug */
@@ -3283,6 +3283,16 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx)
SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
small_prim_filter_cntl);
}
+
+ /* The exclusion bits can be set to improve rasterization efficiency
+ * if no sample lies on the pixel boundary (-8 sample offset).
+ */
+ bool exclusion = sctx->chip_class >= CIK &&
+ (!rs->multisample_enable || nr_samples != 16);
+ radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
+ SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
+ S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
+ S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
}
static bool si_out_of_order_rasterization(struct si_context *sctx)
@@ -4861,9 +4871,6 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
S_008A14_CLIP_VTX_REORDER_ENA(1));
- if (!has_clear_state)
- si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
-
/* CLEAR_STATE doesn't clear these correctly on certain generations.
* I don't know why. Deduced by trial and error.
*/
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 173e210a5a..c3b56ff12f 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -262,6 +262,7 @@ enum si_tracked_reg {
SI_TRACKED_DB_EQAA,
SI_TRACKED_PA_SC_MODE_CNTL_1,
+ SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
SI_TRACKED_PA_CL_VS_OUT_CNTL,
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