Mesa (staging/18.2): radv: Emit enqueued pipeline barriers on event write.

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Module: Mesa
Branch: staging/18.2
Commit: a0aa50c3f68d1ba3fd8f15acb59a8e2c73ba9a2b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0aa50c3f68d1ba3fd8f15acb59a8e2c73ba9a2b

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Oct 23 10:54:24 2018 +0200

radv: Emit enqueued pipeline barriers on event write.

Since the CPU can read them we need to execute any GPU->CPU
flushes before the event is written.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit d41c3cc01314fd2586ad2392a05647197d04c28d)

---

 src/amd/vulkan/radv_cmd_buffer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8b7691eda0..dae6440689 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4347,6 +4347,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
 	struct radeon_cmdbuf *cs = cmd_buffer->cs;
 	uint64_t va = radv_buffer_get_va(event->bo);
 
+	si_emit_cache_flush(cmd_buffer);
+
 	radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
 
 	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);