Mesa (master): freedreno/a6xx: Move stencil/depth/alpha state to IB
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Fri Oct 26 22:11:41 UTC 2018
Module: Mesa
Branch: master
Commit: 01194cd5826fb58a4f9464594850ffc3f4ae6073
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01194cd5826fb58a4f9464594850ffc3f4ae6073
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Wed Oct 24 12:02:00 2018 -0700
freedreno/a6xx: Move stencil/depth/alpha state to IB
Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
---
src/gallium/drivers/freedreno/a6xx/fd6_context.c | 1 +
src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 18 ++--------
src/gallium/drivers/freedreno/a6xx/fd6_emit.h | 1 +
src/gallium/drivers/freedreno/a6xx/fd6_zsa.c | 43 ++++++++++++++++++++++++
src/gallium/drivers/freedreno/a6xx/fd6_zsa.h | 7 ++++
5 files changed, 55 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.c b/src/gallium/drivers/freedreno/a6xx/fd6_context.c
index b55b6f6934..3282b7d86c 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_context.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.c
@@ -107,6 +107,7 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
/* fd_context_init overwrites delete_rasterizer_state, so set this
* here. */
pctx->delete_rasterizer_state = fd6_rasterizer_state_delete;
+ pctx->delete_depth_stencil_alpha_state = fd6_depth_stencil_alpha_state_delete;
fd6_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 7d86510244..1c7f549ee4 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -628,23 +628,11 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
if (dirty & FD_DIRTY_ZSA) {
struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
- uint32_t rb_alpha_control = zsa->rb_alpha_control;
if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
- rb_alpha_control &= ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST;
-
- OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
- OUT_RING(ring, rb_alpha_control);
-
- OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
- OUT_RING(ring, zsa->rb_stencil_control);
-
- OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
- OUT_RING(ring, zsa->rb_depth_cntl);
-
- OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
- OUT_RING(ring, zsa->rb_stencilmask);
- OUT_RING(ring, zsa->rb_stencilwrmask);
+ fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
+ else
+ fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
}
if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
index 79b77ecedc..a86ef0200f 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
@@ -54,6 +54,7 @@ enum fd6_state_id {
FD6_GROUP_VS_TEX,
FD6_GROUP_FS_TEX,
FD6_GROUP_RASTERIZER,
+ FD6_GROUP_ZSA,
};
struct fd6_state_group {
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
index 01599bb1b6..290c8eb929 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
@@ -38,6 +38,7 @@ void *
fd6_zsa_state_create(struct pipe_context *pctx,
const struct pipe_depth_stencil_alpha_state *cso)
{
+ struct fd_context *ctx = fd_context(pctx);
struct fd6_zsa_stateobj *so;
so = CALLOC_STRUCT(fd6_zsa_stateobj);
@@ -121,5 +122,47 @@ fd6_zsa_state_create(struct pipe_context *pctx,
// A6XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
+ so->stateobj = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
+ struct fd_ringbuffer *ring = so->stateobj;
+
+ OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
+ OUT_RING(ring, so->rb_alpha_control);
+
+ OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
+ OUT_RING(ring, so->rb_stencil_control);
+
+ OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
+ OUT_RING(ring, so->rb_depth_cntl);
+
+ OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
+ OUT_RING(ring, so->rb_stencilmask);
+ OUT_RING(ring, so->rb_stencilwrmask);
+
+ so->stateobj_no_alpha = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
+ ring = so->stateobj_no_alpha;
+
+ OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
+ OUT_RING(ring, so->rb_alpha_control & ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST);
+
+ OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
+ OUT_RING(ring, so->rb_stencil_control);
+
+ OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
+ OUT_RING(ring, so->rb_depth_cntl);
+
+ OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
+ OUT_RING(ring, so->rb_stencilmask);
+ OUT_RING(ring, so->rb_stencilwrmask);
+
return so;
}
+
+void
+fd6_depth_stencil_alpha_state_delete(struct pipe_context *pctx, void *hwcso)
+{
+ struct fd6_zsa_stateobj *so = hwcso;
+
+ fd_ringbuffer_del(so->stateobj);
+ fd_ringbuffer_del(so->stateobj_no_alpha);
+ FREE(hwcso);
+}
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
index ca777e0f74..996158c383 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
@@ -45,6 +45,9 @@ struct fd6_zsa_stateobj {
uint32_t gras_lrz_cntl;
uint32_t rb_lrz_cntl;
bool lrz_write;
+
+ struct fd_ringbuffer *stateobj;
+ struct fd_ringbuffer *stateobj_no_alpha;
};
static inline struct fd6_zsa_stateobj *
@@ -56,4 +59,8 @@ fd6_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa)
void * fd6_zsa_state_create(struct pipe_context *pctx,
const struct pipe_depth_stencil_alpha_state *cso);
+void fd6_depth_stencil_alpha_state_delete(struct pipe_context *pctx,
+ void *hwcso);
+
#endif /* FD6_ZSA_H_ */
+
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