Mesa (staging/18.2): intel/blorp: Define the clear value bounds for HiZ clears

[GitLab Mirror]

Module: Mesa
Branch: staging/18.2
Commit: aaff8c7a0ed55d71e9dd0a6fef6905d6a2536c3f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aaff8c7a0ed55d71e9dd0a6fef6905d6a2536c3f

Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Oct 25 14:08:52 2018 -0700

intel/blorp: Define the clear value bounds for HiZ clears

Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:

./bin/depthstencil-render-miplevels 146 d=z32f_s8

Jason found this to fix incorrect clearing on SKL.

Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b
       ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 5bcf479524b96554cab7d2429dacf650b4054638)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

Conflicts:
	src/intel/blorp/blorp_genX_exec.h

---

 src/intel/blorp/blorp_genX_exec.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index bd9a6ae755..6da2485ad0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1637,6 +1637,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
     */
    blorp_emit(batch, GENX(3DSTATE_WM), wm);
 
+   /* From the BDW PRM Volume 7, Depth Buffer Clear:
+    *
+    *    The clear value must be between the min and max depth values
+    *    (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
+    *    D32_FLOAT, then +/-DENORM values are also allowed.
+    *
+    * Set the bounds to match our hardware limits, [0.0, 1.0].
+    */
+   if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {
+      assert(params->depth.clear_color.f32[0] >= 0.0f);
+      assert(params->depth.clear_color.f32[0] <= 1.0f);
+      blorp_emit_cc_viewport(batch);
+   }
+
    /* If we can't alter the depth stencil config and multiple layers are
     * involved, the HiZ op will fail. This is because the op requires that a
     * new config is emitted for each additional layer.