Mesa (master): intel/genxml: turn SLM Enable bit into boolean

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Module: Mesa
Branch: master
Commit: 69874e9a6a61d1af92e4d70adaefe1308582c3a1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69874e9a6a61d1af92e4d70adaefe1308582c3a1

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Fri Sep  7 11:55:45 2018 +0100

intel/genxml: turn SLM Enable bit into boolean

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

---

 src/intel/genxml/gen10.xml | 2 +-
 src/intel/genxml/gen8.xml  | 2 +-
 src/intel/genxml/gen9.xml  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 541e440571..abd5da297d 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3546,7 +3546,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 330366b7ed..d42c63aabd 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3199,7 +3199,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 318ae89d5e..ca26825450 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3484,7 +3484,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>