Mesa (master): radv: Add non-uniform indexing lowering.

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Module: Mesa
Branch: master
Commit: 028ce527395642b68612d10c6030be5d4706a65e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=028ce527395642b68612d10c6030be5d4706a65e

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sun Apr  7 23:57:58 2019 +0200

radv: Add non-uniform indexing lowering.

This patch does it as late as possible so the potential extra
basic blocks don't inhibit other optimizations.

Big thanks to Jason for writing the lowering pass.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

---

 src/amd/vulkan/radv_device.c   | 14 +++++++-------
 src/amd/vulkan/radv_pipeline.c |  5 +++++
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5baf6aad58d..dacaac173ae 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -817,13 +817,13 @@ void radv_GetPhysicalDeviceFeatures2(
 			features->shaderInputAttachmentArrayDynamicIndexing = true;
 			features->shaderUniformTexelBufferArrayDynamicIndexing = true;
 			features->shaderStorageTexelBufferArrayDynamicIndexing = true;
-			features->shaderUniformBufferArrayNonUniformIndexing = false;
-			features->shaderSampledImageArrayNonUniformIndexing = false;
-			features->shaderStorageBufferArrayNonUniformIndexing = false;
-			features->shaderStorageImageArrayNonUniformIndexing = false;
-			features->shaderInputAttachmentArrayNonUniformIndexing = false;
-			features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
-			features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
+			features->shaderUniformBufferArrayNonUniformIndexing = true;
+			features->shaderSampledImageArrayNonUniformIndexing = true;
+			features->shaderStorageBufferArrayNonUniformIndexing = true;
+			features->shaderStorageImageArrayNonUniformIndexing = true;
+			features->shaderInputAttachmentArrayNonUniformIndexing = true;
+			features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
+			features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
 			features->descriptorBindingUniformBufferUpdateAfterBind = true;
 			features->descriptorBindingSampledImageUpdateAfterBind = true;
 			features->descriptorBindingStorageImageUpdateAfterBind = true;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d96ae9a4223..619b5a506ad 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2178,6 +2178,11 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 	for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
 		if (nir[i]) {
 			NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
+			NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
+			                   nir_lower_non_uniform_ubo_access |
+			                   nir_lower_non_uniform_ssbo_access |
+			                   nir_lower_non_uniform_texture_access |
+			                   nir_lower_non_uniform_image_access);
 		}
 
 		if (radv_can_dump_shader(device, modules[i], false))