Mesa (master): vc4: Split UBO0 and UBO1 address uniform handling.

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Module: Mesa
Branch: master
Commit: 0204fb77e0133f9e365bd9d7749984b3421bbed5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0204fb77e0133f9e365bd9d7749984b3421bbed5

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Apr  8 21:39:08 2019 -0700

vc4: Split UBO0 and UBO1 address uniform handling.

I'm going to extend how UBO0 works in a moment.

---

 src/gallium/drivers/vc4/vc4_program.c  |  6 +++---
 src/gallium/drivers/vc4/vc4_qir.h      |  3 ++-
 src/gallium/drivers/vc4/vc4_uniforms.c | 30 +++++++++++++++---------------
 3 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index 135d4bc7198..4c284b6cd7c 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -135,7 +135,7 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
 
         qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
                      indirect_offset,
-                     qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
+                     qir_uniform(c, QUNIFORM_UBO0_ADDR, 0));
 
         c->num_texture_samples++;
 
@@ -147,7 +147,7 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
 static struct qreg
 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
 {
-        unsigned buffer_index = nir_src_as_uint(intr->src[0]);
+        int buffer_index = nir_src_as_uint(intr->src[0]);
         assert(buffer_index == 1);
         assert(c->stage == QSTAGE_FRAG);
 
@@ -160,7 +160,7 @@ vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
 
         qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
                      offset,
-                     qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index));
+                     qir_uniform(c, QUNIFORM_UBO1_ADDR, 0));
 
         c->num_texture_samples++;
 
diff --git a/src/gallium/drivers/vc4/vc4_qir.h b/src/gallium/drivers/vc4/vc4_qir.h
index 1aa5f652fbc..17a0d0febc0 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -269,7 +269,8 @@ enum quniform_contents {
 
         QUNIFORM_TEXTURE_MSAA_ADDR,
 
-        QUNIFORM_UBO_ADDR,
+        QUNIFORM_UBO0_ADDR,
+        QUNIFORM_UBO1_ADDR,
 
         QUNIFORM_TEXRECT_SCALE_X,
         QUNIFORM_TEXRECT_SCALE_Y,
diff --git a/src/gallium/drivers/vc4/vc4_uniforms.c b/src/gallium/drivers/vc4/vc4_uniforms.c
index 3801fbc8f6b..d12f5667045 100644
--- a/src/gallium/drivers/vc4/vc4_uniforms.c
+++ b/src/gallium/drivers/vc4/vc4_uniforms.c
@@ -271,22 +271,21 @@ vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
                                                   data);
                         break;
 
-                case QUNIFORM_UBO_ADDR:
-                        if (data == 0) {
-                                cl_aligned_reloc(job, &job->uniforms,
-                                                 &uniforms, ubo, 0);
-                        } else {
-                                struct pipe_constant_buffer *c =
-                                        &cb->cb[data];
-                                struct vc4_resource *rsc =
-                                        vc4_resource(c->buffer);
-
-                                cl_aligned_reloc(job, &job->uniforms,
-                                                 &uniforms,
-                                                 rsc->bo, c->buffer_offset);
-                        }
+                case QUNIFORM_UBO0_ADDR:
+                        cl_aligned_reloc(job, &job->uniforms,
+                                         &uniforms, ubo, data);
                         break;
 
+                case QUNIFORM_UBO1_ADDR: {
+                        struct vc4_resource *rsc =
+                                vc4_resource(cb->cb[1].buffer);
+
+                        cl_aligned_reloc(job, &job->uniforms,
+                                         &uniforms,
+                                         rsc->bo, cb->cb[1].buffer_offset);
+                        break;
+                }
+
                 case QUNIFORM_TEXTURE_MSAA_ADDR:
                         write_texture_msaa_addr(job, &uniforms, texstate, data);
                         break;
@@ -390,7 +389,8 @@ vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader)
                 case QUNIFORM_UNIFORMS_ADDRESS:
                         break;
                 case QUNIFORM_UNIFORM:
-                case QUNIFORM_UBO_ADDR:
+                case QUNIFORM_UBO0_ADDR:
+                case QUNIFORM_UBO1_ADDR:
                         dirty |= VC4_DIRTY_CONSTBUF;
                         break;