Mesa (master): intel/nir: Take a nir_tex_instr and src index in brw_texture_offset

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 6b1c398bcbf1dd1a11db8895e5d642ac3267bdad
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b1c398bcbf1dd1a11db8895e5d642ac3267bdad

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Wed Mar 27 17:34:10 2019 -0500

intel/nir: Take a nir_tex_instr and src index in brw_texture_offset

This makes things a bit simpler and it's also more robust because it no
longer has a hard dependency on the offset being a 32-bit value.

---

 src/intel/compiler/brw_fs_nir.cpp   | 10 ++--------
 src/intel/compiler/brw_shader.cpp   | 24 ++++++++++++++++--------
 src/intel/compiler/brw_shader.h     |  3 +--
 src/intel/compiler/brw_vec4_nir.cpp | 11 ++---------
 4 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 875f3fac66c..ed8c479ca40 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5062,14 +5062,8 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
          break;
 
       case nir_tex_src_offset: {
-         nir_const_value *const_offset =
-            nir_src_as_const_value(instr->src[i].src);
-         assert(nir_src_bit_size(instr->src[i].src) == 32);
-         unsigned offset_bits = 0;
-         if (const_offset &&
-             brw_texture_offset(const_offset->i32,
-                                nir_tex_instr_src_size(instr, i),
-                                &offset_bits)) {
+         uint32_t offset_bits = 0;
+         if (brw_texture_offset(instr, i, &offset_bits)) {
             header_bits |= offset_bits;
          } else {
             srcs[TEX_LOGICAL_SRC_TG4_OFFSET] =
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 1b0eeed8415..06f613cf6b5 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -129,14 +129,13 @@ brw_math_function(enum opcode op)
 }
 
 bool
-brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
+brw_texture_offset(const nir_tex_instr *tex, unsigned src,
+                   uint32_t *offset_bits_out)
 {
-   if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
+   if (!nir_src_is_const(tex->src[src].src))
+      return false;
 
-   /* offset out of bounds; caller will handle it. */
-   for (unsigned i = 0; i < num_components; i++)
-      if (offsets[i] > 7 || offsets[i] < -8)
-         return false;
+   const unsigned num_components = nir_tex_instr_src_size(tex, src);
 
    /* Combine all three offsets into a single unsigned dword:
     *
@@ -144,11 +143,20 @@ brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
     *    bits  7:4 - V Offset (Y component)
     *    bits  3:0 - R Offset (Z component)
     */
-   *offset_bits = 0;
+   uint32_t offset_bits = 0;
    for (unsigned i = 0; i < num_components; i++) {
+      int offset = nir_src_comp_as_int(tex->src[src].src, i);
+
+      /* offset out of bounds; caller will handle it. */
+      if (offset > 7 || offset < -8)
+         return false;
+
       const unsigned shift = 4 * (2 - i);
-      *offset_bits |= (offsets[i] << shift) & (0xF << shift);
+      offset_bits |= (offset << shift) & (0xF << shift);
    }
+
+   *offset_bits_out = offset_bits;
+
    return true;
 }
 
diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index 45ff19832b7..61b5cd6fad3 100644
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -243,8 +243,7 @@ public:
    virtual void invalidate_live_intervals() = 0;
 };
 
-bool brw_texture_offset(int *offsets,
-                        unsigned num_components,
+bool brw_texture_offset(const nir_tex_instr *tex, unsigned src,
                         uint32_t *offset_bits);
 
 #else
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 3576074fc36..53a0d97117c 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -2061,19 +2061,12 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
          break;
       }
 
-      case nir_tex_src_offset: {
-         nir_const_value *const_offset =
-            nir_src_as_const_value(instr->src[i].src);
-         assert(nir_src_bit_size(instr->src[i].src) == 32);
-         if (!const_offset ||
-             !brw_texture_offset(const_offset->i32,
-                                 nir_tex_instr_src_size(instr, i),
-                                 &constant_offset)) {
+      case nir_tex_src_offset:
+         if (!brw_texture_offset(instr, i, &constant_offset)) {
             offset_value =
                get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2);
          }
          break;
-      }
 
       case nir_tex_src_texture_offset: {
          /* Emit code to evaluate the actual indexing expression */